| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 585 FLOG, FLOG2, FLOG10, FEXP, FEXP2, enumerator
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| H A D | BasicTTIImpl.h | 1167 ISDs.push_back(ISD::FEXP2);
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| H A D | TargetLowering.h | 856 case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break; in getStrictFPOperationAction()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 209 case ISD::FEXP2: return "fexp2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 85 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
1079 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
1896 case ISD::FEXP2: in PromoteFloatResult()
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| H A D | LegalizeVectorOps.cpp | 401 case ISD::FEXP2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 84 case ISD::FEXP2: in ScalarizeVectorResult()
769 case ISD::FEXP2: in SplitVectorResult()
2512 case ISD::FEXP2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 3914 case ISD::FEXP2: in ConvertNodeToLibcall()
4379 case ISD::FEXP2: in PromoteNode()
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| H A D | SelectionDAG.cpp | 3844 case ISD::FEXP2: in isKnownNeverNaN()
7649 case ISD::STRICT_FEXP2: NewOpc = ISD::FEXP2; IsUnary = true; break; in mutateStrictFPToFP()
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| H A D | SelectionDAGBuilder.cpp | 4843 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); in expandExp2()
7125 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 153 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in MipsSETargetLowering()
384 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1856 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsMSAInstrInfo.td | 2044 // 1.0 when we only need to match ISD::FEXP2.
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 684 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 303 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
450 setOperationAction(ISD::FEXP2, VT, Expand); in AMDGPUTargetLowering()
2261 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags()); in lowerFEXP()
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| H A D | SIISelLowering.cpp | 7623 case ISD::FEXP2: in fp16SrcZerosHighBits()
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 437 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 356 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in AArch64TargetLowering()
357 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand); in AArch64TargetLowering()
358 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand); in AArch64TargetLowering()
772 setOperationAction(ISD::FEXP2, VT, Expand); in addTypeForNEON()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1424 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 598 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
615 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
631 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
757 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 606 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
921 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); in PPCTargetLowering()
966 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand); in PPCTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 682 setOperationAction(ISD::FEXP2, MVT::f80, Expand); in X86TargetLowering()
699 setOperationAction(ISD::FEXP2, VT, Expand); in X86TargetLowering()
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