| /freebsd-12.1/contrib/one-true-awk/ |
| H A D | awk.h | 117 #define FEXP 3 macro
|
| H A D | lex.c | 61 { "exp", FEXP, BLTIN },
|
| H A D | run.c | 1500 case FEXP: in bltin()
|
| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 585 FLOG, FLOG2, FLOG10, FEXP, FEXP2, enumerator
|
| H A D | BasicTTIImpl.h | 1164 ISDs.push_back(ISD::FEXP);
|
| H A D | TargetLowering.h | 855 case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break; in getStrictFPOperationAction()
|
| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 207 case ISD::FEXP: return "fexp"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 84 case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break; in SoftenFloatResult()
1078 case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break; in ExpandFloatResult()
1895 case ISD::FEXP: in PromoteFloatResult()
|
| H A D | LegalizeVectorOps.cpp | 400 case ISD::FEXP: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 83 case ISD::FEXP: in ScalarizeVectorResult()
768 case ISD::FEXP: in SplitVectorResult()
2511 case ISD::FEXP: in WidenVectorResult()
|
| H A D | LegalizeDAG.cpp | 3901 case ISD::FEXP: in ConvertNodeToLibcall()
4378 case ISD::FEXP: in PromoteNode()
|
| H A D | SelectionDAG.cpp | 3843 case ISD::FEXP: in isKnownNeverNaN()
7648 case ISD::STRICT_FEXP: NewOpc = ISD::FEXP; IsUnary = true; break; in mutateStrictFPToFP()
|
| H A D | SelectionDAGBuilder.cpp | 4546 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); in expandExp()
|
| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 683 setOperationAction(ISD::FEXP , VT, Expand); in initActions()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 318 setOperationAction(ISD::FEXP, MVT::f32, Custom); in AMDGPUTargetLowering()
451 setOperationAction(ISD::FEXP, VT, Expand); in AMDGPUTargetLowering()
1161 case ISD::FEXP: in LowerOperation()
|
| H A D | SIISelLowering.cpp | 351 setOperationAction(ISD::FEXP, MVT::f16, Custom); in SITargetLowering()
632 setOperationAction(ISD::FEXP, MVT::v2f16, Custom); in SITargetLowering()
7622 case ISD::FEXP: in fp16SrcZerosHighBits()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 353 setOperationAction(ISD::FEXP, MVT::f16, Promote); in AArch64TargetLowering()
354 setOperationAction(ISD::FEXP, MVT::v4f16, Expand); in AArch64TargetLowering()
355 setOperationAction(ISD::FEXP, MVT::v8f16, Expand); in AArch64TargetLowering()
771 setOperationAction(ISD::FEXP, VT, Expand); in addTypeForNEON()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1424 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 597 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); in ARMTargetLowering()
614 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); in ARMTargetLowering()
630 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
756 setOperationAction(ISD::FEXP, MVT::f64, Expand); in ARMTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 152 setOperationAction(ISD::FEXP, MVT::f16, Promote); in MipsSETargetLowering()
|
| H A D | MipsISelLowering.cpp | 447 setOperationAction(ISD::FEXP, MVT::f32, Expand); in MipsTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 605 setOperationAction(ISD::FEXP, VT, Expand); in PPCTargetLowering()
920 setOperationAction(ISD::FEXP , MVT::v4f64, Expand); in PPCTargetLowering()
965 setOperationAction(ISD::FEXP , MVT::v4f32, Expand); in PPCTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 681 setOperationAction(ISD::FEXP, MVT::f80, Expand); in X86TargetLowering()
698 setOperationAction(ISD::FEXP, VT, Expand); in X86TargetLowering()
1848 {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG, in X86TargetLowering()
|