| /freebsd-12.1/contrib/one-true-awk/ |
| H A D | awk.h | 124 #define FCOS 10 macro
|
| H A D | lex.c | 56 { "cos", FCOS, BLTIN },
|
| H A D | run.c | 1506 case FCOS: in bltin()
|
| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 584 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| H A D | BasicTTIImpl.h | 1161 ISDs.push_back(ISD::FCOS);
|
| H A D | TargetLowering.h | 854 case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break; in getStrictFPOperationAction()
|
| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 192 case ISD::FCOS: return "fcos"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 82 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; in SoftenFloatResult()
1076 case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break; in ExpandFloatResult()
1894 case ISD::FCOS: in PromoteFloatResult()
|
| H A D | LegalizeDAG.cpp | 2246 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3071 case ISD::FCOS: { in ExpandNode()
3080 if (Node->getOpcode() == ISD::FCOS) in ExpandNode()
3852 case ISD::FCOS: in ConvertNodeToLibcall()
4373 case ISD::FCOS: in PromoteNode()
|
| H A D | LegalizeVectorOps.cpp | 394 case ISD::FCOS: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 82 case ISD::FCOS: in ScalarizeVectorResult()
767 case ISD::FCOS: in SplitVectorResult()
2510 case ISD::FCOS: in WidenVectorResult()
|
| H A D | SelectionDAG.cpp | 3836 case ISD::FCOS: { in isKnownNeverNaN()
7647 case ISD::STRICT_FCOS: NewOpc = ISD::FCOS; IsUnary = true; break; in mutateStrictFPToFP()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 140 setOperationAction(ISD::FCOS, MVT::f32, Custom); in R600TargetLowering()
485 case ISD::FCOS: in LowerOperation()
770 case ISD::FCOS: in LowerTrig()
|
| H A D | SIISelLowering.cpp | 417 setOperationAction(ISD::FCOS, MVT::f32, Custom); in SITargetLowering()
479 setOperationAction(ISD::FCOS, MVT::f16, Promote); in SITargetLowering()
3633 case ISD::FCOS: in LowerOperation()
6999 case ISD::FCOS: in LowerTrig()
7616 case ISD::FCOS: in fp16SrcZerosHighBits()
7773 case ISD::FCOS: in isCanonicalized()
|
| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 97 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1617 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1622 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1627 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 213 setOperationAction(ISD::FCOS, MVT::f128, Expand); in AArch64TargetLowering()
324 setOperationAction(ISD::FCOS, MVT::f32, Expand); in AArch64TargetLowering()
325 setOperationAction(ISD::FCOS, MVT::f64, Expand); in AArch64TargetLowering()
344 setOperationAction(ISD::FCOS, MVT::f16, Promote); in AArch64TargetLowering()
345 setOperationAction(ISD::FCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
346 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
627 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
766 setOperationAction(ISD::FCOS, VT, Expand); in addTypeForNEON()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1377 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1423 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 122 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM}; in RISCVTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 438 setOperationAction(ISD::FCOS, MVT::f32, Expand); in MipsTargetLowering()
439 setOperationAction(ISD::FCOS, MVT::f64, Expand); in MipsTargetLowering()
|
| H A D | MipsSEISelLowering.cpp | 142 setOperationAction(ISD::FCOS, MVT::f16, Promote); in MipsSETargetLowering()
|
| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 436 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
|
| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 266 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
271 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
608 setOperationAction(ISD::FCOS, VT, Expand); in PPCTargetLowering()
864 setOperationAction(ISD::FCOS , MVT::f128, Expand); in PPCTargetLowering()
915 setOperationAction(ISD::FCOS , MVT::v4f64, Expand); in PPCTargetLowering()
960 setOperationAction(ISD::FCOS , MVT::v4f32, Expand); in PPCTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 592 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
609 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); in ARMTargetLowering()
625 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
751 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
1076 setOperationAction(ISD::FCOS, MVT::f32, Expand); in ARMTargetLowering()
1077 setOperationAction(ISD::FCOS, MVT::f64, Expand); in ARMTargetLowering()
|
| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 566 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, in NVPTXTargetLowering()
|