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Searched refs:ExtOp (Results 1 – 13 of 13) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4209 unsigned ExtOp, TruncOp; in PromoteNode() local
4211 ExtOp = ISD::BITCAST; in PromoteNode()
4218 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4222 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
4226 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
4258 unsigned ExtOp, TruncOp; in PromoteNode() local
4261 ExtOp = ISD::BITCAST; in PromoteNode()
4264 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4267 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4298 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
[all …]
H A DDAGCombiner.cpp12039 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
12041 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1533 MachineOperand ExtOp(EV); in insertInitializer() local
1544 .add(ExtOp); in insertInitializer()
1550 .add(ExtOp); in insertInitializer()
1555 .add(ExtOp) in insertInitializer()
1561 .add(ExtOp); in insertInitializer()
1568 .add(ExtOp) in insertInitializer()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrSSE.td5210 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5215 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5218 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5322 SDNode ExtOp> {
5324 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
5328 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
5330 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
5333 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
5335 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
5338 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
[all …]
H A DX86InstrAVX512.td10009 def : Pat<(v8i32 (ExtOp (loadv8i16 addr:$src))),
10016 def : Pat<(v4i64 (ExtOp (loadv4i32 addr:$src))),
10044 AVX512_pmovx_patterns_base<OpcPrefix, ExtOp> {
10046 def : Pat<(v16i16 (ExtOp (v16i8 VR128X:$src))),
10051 def : Pat<(v8i32 (ExtOp (v8i16 VR128X:$src))),
10054 def : Pat<(v4i64 (ExtOp (v4i32 VR128X:$src))),
10060 def : Pat<(v32i16 (ExtOp (v32i8 VR256X:$src))),
10064 def : Pat<(v16i32 (ExtOp (v16i8 VR128X:$src))),
10069 def : Pat<(v8i64 (ExtOp (v8i16 VR128X:$src))),
10072 def : Pat<(v8i64 (ExtOp (v8i32 VR256X:$src))),
[all …]
H A DX86ISelLowering.cpp16513 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
16516 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
33737 SDValue ExtOp = DAG.getNode(OpCode, dl, MVT::i32, SrcOp, in combineExtractWithShuffle() local
33739 return DAG.getZExtOrTrunc(ExtOp, dl, VT); in combineExtractWithShuffle()
41414 unsigned ExtOp = in combineExtractSubvector() local
41417 return DAG.getNode(ExtOp, SDLoc(N), OpVT, InVec.getOperand(0)); in combineExtractSubvector()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp383 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
384 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
H A DSIISelLowering.cpp8038 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
8040 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
8041 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
8042 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3102 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3115 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3164 SDNode OpNode, SDNode ExtOp, bit Commutable>
3678 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3681 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3746 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3749 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3752 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3910 IntOp, ExtOp, OpNode>;
3913 IntOp, ExtOp, OpNode>;
[all …]
H A DARMISelLowering.cpp9958 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
9959 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DIndVarSimplify.cpp1349 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1350 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5818 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
5819 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6381 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
6382 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
12217 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
12218 if (!ExtOp) in combineBVOfVecSExt()
12221 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGBuiltin.cpp5629 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
5633 if (ExtOp) in packTBLDVectorList()
5634 TblOps.push_back(ExtOp); in packTBLDVectorList()