Searched refs:DivOpc (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1922 unsigned DivOpc; in selectDivRem() local
1928 DivOpc = Mips::SDIV; in selectDivRem()
1932 DivOpc = Mips::UDIV; in selectDivRem()
1941 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4590 unsigned DivOpc; in selectRem() local
4596 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr; in selectRem()
4599 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr; in selectRem()
4615 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false, in selectRem()
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| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 4287 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV; in PerformREMCombine() local
4293 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num && in PerformREMCombine()
4298 DAG.getNode(DivOpc, DL, VT, Num, Den), in PerformREMCombine()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 3156 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; in ExpandNode() local
3164 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { in ExpandNode()
3166 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); in ExpandNode()
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