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Searched refs:DefMI (Results 1 – 25 of 57) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp97 if (DefMI->getParent() != MBB) in getAccDefMI()
99 if (DefMI->isCopyLike()) { in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
114 return DefMI; in getAccDefMI()
152 if (DefMI->getParent() != MBB) in hasLoopHazard()
155 if (DefMI->isPHI()) { in hasLoopHazard()
165 } else if (DefMI->isCopyLike()) { in hasLoopHazard()
168 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
182 return DefMI == MI; in hasLoopHazard()
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H A DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
45 MachineInstr *DefMI = LastMI; in getHazardType() local
58 DefMI = &*I; in getHazardType()
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
64 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
H A DARMBaseInstrInfo.h309 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
316 const MachineInstr &DefMI, unsigned DefIdx,
370 const MachineInstr &DefMI, unsigned DefIdx,
387 const MachineInstr &DefMI, unsigned DefIdx,
391 const MachineInstr &DefMI,
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetSchedule.cpp186 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
190 return TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
199 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
218 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
219 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
243 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
253 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
304 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); in computeOutputLatency()
305 const MachineFunction &MF = *DefMI->getMF(); in computeOutputLatency()
308 return computeInstrLatency(DefMI); in computeOutputLatency()
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H A DLiveRangeEdit.cpp74 assert(DefMI && "Missing instruction"); in checkRematerializable()
76 if (!TII.isTriviallyReMaterializable(*DefMI, aa)) in checkRematerializable()
92 if (!DefMI) in scanRemattable()
94 checkRematerializable(OrigVNI, DefMI, aa); in scanRemattable()
194 if (DefMI && DefMI != MI) in foldAsLoad()
198 DefMI = MI; in foldAsLoad()
208 if (!DefMI || !UseMI) in foldAsLoad()
213 if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI), in foldAsLoad()
220 if (!DefMI->isSafeToMove(nullptr, SawStore)) in foldAsLoad()
236 DefMI->addRegisterDead(LI->reg, nullptr); in foldAsLoad()
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H A DMachineTraceMetrics.cpp628 const MachineInstr *DefMI; member
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
641 DefMI = DefI->getParent(); in DataDep()
776 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
803 if (!Dep.DefMI->isTransient()) in updateDepth()
958 if (!Dep.DefMI->isTransient()) in pushDepHeight()
982 unsigned Reg = DefMI->getOperand(DefOp).getReg(); in addLiveIns()
1119 addLiveIns(Dep.DefMI, Dep.DefOp, Stack); in computeInstrHeights()
1137 LIR.Height = Heights.lookup(DefMI); in computeInstrHeights()
1190 if (!Dep.DefMI->isTransient()) in getPHIDepth()
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H A DRegisterCoalescer.cpp758 if (!DefMI) in removeCopyByCommutingDef()
760 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
808 << *DefMI); in removeCopyByCommutingDef()
821 if (NewMI != DefMI) { in removeCopyByCommutingDef()
825 MBB->erase(DefMI); in removeCopyByCommutingDef()
1031 if (!DefMI || !DefMI->isFullCopy()) { in removePartialRedundancy()
1193 if (!DefMI) in reMaterializeTrivialDef()
1195 if (DefMI->isCopyLike()) { in reMaterializeTrivialDef()
2469 assert(DefMI != nullptr); in analyzeValue()
2577 if (DefMI && in analyzeValue()
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H A DMachineCSE.cpp157 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
158 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
160 unsigned SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
163 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
177 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
181 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
185 DefMI->changeDebugValuesDefReg(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
192 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
H A DPHIElimination.cpp171 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
172 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
175 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
176 DefMI->eraseFromParent(); in runOnMachineFunction()
406 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
407 if (DefMI->isImplicitDef()) in LowerPHINode()
408 ImpDefs.insert(DefMI); in LowerPHINode()
H A DTwoAddressInstructionPass.cpp347 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in getSingleDef()
348 if (DefMI.getParent() != BB || DefMI.isDebugValue()) in getSingleDef()
351 Ret = &DefMI; in getSingleDef()
352 else if (Ret != &DefMI) in getSingleDef()
476 MachineInstr *DefMI = &MI; in isKilled() local
482 if (!isPlainlyKilled(DefMI, Reg, LIS)) in isKilled()
491 DefMI = Begin->getParent(); in isKilled()
1028 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in isDefTooClose()
1029 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) in isDefTooClose()
1031 if (&DefMI == MI) in isDefTooClose()
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H A DDetectDeadLanes.cpp360 const MachineInstr &DefMI = *Def.getParent(); in determineInitialDefinedLanes() local
361 if (lowersToCopies(DefMI)) { in determineInitialDefinedLanes()
378 for (const MachineOperand &MO : DefMI.uses()) { in determineInitialDefinedLanes()
388 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
405 unsigned OpNum = DefMI.getOperandNo(&MO); in determineInitialDefinedLanes()
410 if (DefMI.isImplicitDef() || Def.isDead()) in determineInitialDefinedLanes()
H A DTargetInstrInfo.cpp1077 const MachineInstr &DefMI) const { in defaultDefLatency()
1078 if (DefMI.isTransient()) in defaultDefLatency()
1080 if (DefMI.mayLoad()) in defaultDefLatency()
1082 if (isHighLatencyDef(DefMI.getOpcode())) in defaultDefLatency()
1103 const MachineInstr &DefMI, in hasLowDefLatency() argument
1109 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1117 const MachineInstr &DefMI, in getOperandLatency() argument
1121 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1129 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const { in computeDefOperandLatency()
1133 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp67 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
146 if (MI.getParent() != DefMI.getParent()) in tryToTuneBranch()
152 switch (DefMI.getOpcode()) { in tryToTuneBranch()
198 MachineBasicBlock::iterator I(DefMI), E(MI); in tryToTuneBranch()
205 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
209 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); in tryToTuneBranch()
257 MachineBasicBlock::iterator I(DefMI), E(MI); in tryToTuneBranch()
264 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
268 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); in tryToTuneBranch()
287 DefMI.eraseFromParent(); in tryToTuneBranch()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp344 for (auto DefMI : List) { in chooseBestLEA() local
358 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
365 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
375 BestLEA = DefMI; in chooseBestLEA()
519 MachineInstr *DefMI; in removeRedundantAddrCalc() local
532 DefMI->removeFromParent(); in removeRedundantAddrCalc()
533 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
534 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
537 assert(((InstrPos[DefMI] == 1 && in removeRedundantAddrCalc()
539 InstrPos[DefMI] > in removeRedundantAddrCalc()
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H A DX86CallFrameOptimization.cpp612 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
616 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
617 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
618 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
623 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
627 return &DefMI; in canFoldIntoRegPush()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp307 unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0; in simplifyCode()
325 if (DefMI && (Immed == 0 || Immed == 3)) { in simplifyCode()
378 .add(DefMI->getOperand(1)); in simplifyCode()
406 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() local
407 if (!DefMI) in simplifyCode()
409 unsigned DefOpcode = DefMI->getOpcode(); in simplifyCode()
450 LLVM_DEBUG(DefMI->dump()); in simplifyCode()
451 ToErase = DefMI; in simplifyCode()
469 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() local
473 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
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H A DPPCInstrInfo.h137 MachineInstr &DefMI,
152 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
157 const MachineInstr &DefMI,
161 const MachineInstr &DefMI,
218 const MachineInstr &DefMI, unsigned DefIdx,
229 const MachineInstr &DefMI, in hasLowDefLatency() argument
312 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
H A DPPCVSXSwapRemoval.cpp621 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
622 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
624 int DefIdx = SwapMap[DefMI]; in formWebs()
632 LLVM_DEBUG(DefMI->dump()); in formWebs()
703 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
704 unsigned DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
705 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
715 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
734 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
781 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval()
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H A DPPCInstrInfo.cpp184 if (!DefMI.getParent()) in getOperandLatency()
1372 DefMI.eraseFromParent(); in FoldImmediate()
2325 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) { in getForwardingDefMI()
2439 if (!DefMI) in convertToImmediateForm()
2446 *KilledDef = DefMI; in convertToImmediateForm()
2457 if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) || in convertToImmediateForm()
2655 LLVM_DEBUG(DefMI->dump()); in convertToImmediateForm()
3163 RegMO = &DefMI.getOperand(1); in isDefMIElgibleForForwarding()
3164 ImmMO = &DefMI.getOperand(2); in isDefMIElgibleForForwarding()
3204 if ((&*It) == &DefMI) in isRegElgibleForForwarding()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp283 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
285 assert(DefMI); in isCallViaRegister()
289 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
292 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
298 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
299 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
301 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h138 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef() local
159 markInstAndDefDead(MI, *DefMI, DeadInsts); in tryFoldImplicitDef()
283 void markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI, in markInstAndDefDead() argument
297 while (PrevMI != &DefMI) { in markInstAndDefDead()
302 if (TmpDef != &DefMI) { in markInstAndDefDead()
311 if (PrevMI == &DefMI && MRI.hasOneUse(DefMI.getOperand(0).getReg())) in markInstAndDefDead()
312 DeadInsts.push_back(&DefMI); in markInstAndDefDead()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp211 auto *DefMI = MRI.getVRegDef(Reg); in getOpcodeDef() local
212 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); in getOpcodeDef()
215 while (DefMI->getOpcode() == TargetOpcode::COPY) { in getOpcodeDef()
216 unsigned SrcReg = DefMI->getOperand(1).getReg(); in getOpcodeDef()
220 DefMI = MRI.getVRegDef(SrcReg); in getOpcodeDef()
222 return DefMI->getOpcode() == Opcode ? DefMI : nullptr; in getOpcodeDef()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp499 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); in optimizeSelect() local
500 bool Invert = !DefMI; in optimizeSelect()
501 if (!DefMI) in optimizeSelect()
502 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); in optimizeSelect()
503 if (!DefMI) in optimizeSelect()
515 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
518 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
521 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
539 SeenMIs.erase(DefMI); in optimizeSelect()
545 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h171 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
195 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
H A DTargetInstrInfo.h1317 MachineInstr *&DefMI) const { in optimizeLoadInstr() argument
1327 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
1360 const MachineInstr &DefMI, unsigned DefIdx,
1378 const MachineInstr &DefMI) const;
1381 const MachineInstr &DefMI) const;
1393 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1402 const MachineInstr &DefMI,

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