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Searched refs:DefIdx (Results 1 – 25 of 41) sorted by relevance

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/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrItineraries.h182 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
186 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
188 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
196 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
203 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
208 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
218 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
H A DMCSubtargetInfo.h130 unsigned DefIdx) const { in getWriteLatencyEntry() argument
131 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
134 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h60 const MachineInstr &MI, unsigned DefIdx,
73 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
89 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
316 const MachineInstr &DefMI, unsigned DefIdx,
320 SDNode *DefNode, unsigned DefIdx,
350 unsigned DefIdx, unsigned DefAlign) const;
354 unsigned DefIdx, unsigned DefAlign) const;
365 unsigned DefIdx, unsigned DefAlign,
370 const MachineInstr &DefMI, unsigned DefIdx,
387 const MachineInstr &DefMI, unsigned DefIdx,
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H A DARMBaseInstrInfo.cpp3543 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3546 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3600 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3603 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3718 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
3830 DefIdx = Idx; in getBundledDefMI()
4046 unsigned DefIdx, in getOperandLatency() argument
4053 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
4488 unsigned DefIdx, in hasHighOperandLatency() argument
5016 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h206 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
207 ++j, ++DefIdx) in tryCombineMerges()
208 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineMerges()
226 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
228 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineMerges()
232 Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs); in tryCombineMerges()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetSchedule.cpp159 unsigned DefIdx = 0; in findDefIdx() local
163 ++DefIdx; in findDefIdx()
165 return DefIdx; in findDefIdx()
219 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
220 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
223 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
245 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
H A DTargetInstrInfo.cpp1040 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1110 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1118 unsigned DefIdx, in getOperandLatency() argument
1143 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1149 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1153 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
1170 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs() argument
1176 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1180 assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def"); in getExtractSubregInputs()
1195 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs() argument
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H A DPeepholeOptimizer.cpp370 unsigned DefIdx = 0; member in __anon649c77ce0111::ValueTracker
424 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1814 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1835 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1874 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1923 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1952 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
2048 assert(((Def->getOperand(DefIdx).isDef() && in getNextSourceImpl()
2049 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2051 Def->getOperand(DefIdx).isImplicit()) && in getNextSourceImpl()
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H A DLiveRangeCalc.cpp68 SlotIndex DefIdx = in createDeadDef() local
72 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
199 unsigned DefIdx; in extendToUses() local
202 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
205 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
H A DMachineVerifier.cpp1283 unsigned DefIdx; in visitMachineOperand() local
1285 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
1286 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
1505 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
1507 if (VNI->def != DefIdx) { in checkLivenessAtDef()
1514 report_context(DefIdx); in checkLivenessAtDef()
1522 report_context(DefIdx); in checkLivenessAtDef()
1526 LiveQueryResult LRQ = LR.Query(DefIdx); in checkLivenessAtDef()
1677 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
1678 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
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H A DLiveRangeEdit.cpp150 SlotIndex DefIdx; in canRematerializeAt() local
152 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
159 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineInstr.cpp281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
282 if (DefIdx != -1) in addOperand()
283 tieOperands(DefIdx, OpNo); in addOperand()
831 unsigned DefIdx; in getRegClassConstraint() local
832 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
833 OpIdx = DefIdx; in getRegClassConstraint()
1036 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1037 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1044 if (DefIdx < TiedMax) in tieOperands()
1045 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
H A DTargetRegisterInfo.cpp361 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
364 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCSchedule.cpp44 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
45 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
48 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h464 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
482 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
502 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1046 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1060 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1074 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1348 SDNode *DefNode, unsigned DefIdx,
1360 const MachineInstr &DefMI, unsigned DefIdx,
1393 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1403 unsigned DefIdx) const;
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp624 int DefIdx = SwapMap[DefMI]; in formWebs() local
625 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
629 SwapVector[DefIdx].VSEId, in formWebs()
705 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
707 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
708 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
714 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
781 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
782 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h218 const MachineInstr &DefMI, unsigned DefIdx,
222 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
224 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
230 unsigned DefIdx) const override { in hasLowDefLatency() argument
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp127 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands() local
128 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) in constrainSelectedInstRegOperands()
129 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()
/freebsd-12.1/contrib/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp213 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
214 DefIdx != DefEnd; ++DefIdx) { in getLatency()
217 DefIdx); in getLatency()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx; variable
160 return DefIdx-1; in GetIdx()
H A DScheduleDAGSDNodes.cpp553 DefIdx = 0; in InitNodeNumDefs()
559 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
567 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
568 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
570 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
571 ++DefIdx; in Advance()
633 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
637 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp205 unsigned DefIdx = 0; in tryInlineAsm() local
209 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in tryInlineAsm()
210 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
296 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in tryInlineAsm()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp426 int DefIdx = -1; in restoreLatency() local
430 DefIdx = OpNum; in restoreLatency()
432 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
439 DefIdx, *DstI, OpNum)); in restoreLatency()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp521 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
523 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
524 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()

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