1030                                    SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
1040     return ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
1042   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1104                                        unsigned DefIdx) const {  in hasLowDefLatency()
1110   int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
1118                                        unsigned DefIdx,  in getOperandLatency()  argument
1123   return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
1143     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceInputs()  argument
1149     return getRegSequenceLikeInputs(MI, DefIdx, InputRegs);  in getRegSequenceInputs()
1153   assert(DefIdx == 0 && "REG_SEQUENCE only has one def");  in getRegSequenceInputs()
1170     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregInputs()  argument
1176     return getExtractSubregLikeInputs(MI, DefIdx, InputReg);  in getExtractSubregInputs()
1180   assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def");  in getExtractSubregInputs()
1195     const MachineInstr &MI, unsigned DefIdx,  in getInsertSubregInputs()  argument
1201     return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg);  in getInsertSubregInputs()
1205   assert(DefIdx == 0 && "INSERT_SUBREG only has one def");  in getInsertSubregInputs()