| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.h | 32 enum CondCodes { enum
70 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
71 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
72 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
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| H A D | AVRInstrInfo.cpp | 195 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { in getBrCond()
218 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const { in getCondFromBranchOpc()
241 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const { in getOppositeCondition()
325 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); in analyzeBranch()
387 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
422 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
471 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 65 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
142 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
190 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); in MoveCopyOutOfITBlock()
207 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
230 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
247 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); in InsertITInstructions()
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| H A D | ARMBaseInstrInfo.h | 151 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
153 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() in getPredicate()
455 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
511 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
533 ARMCC::CondCodes Pred, unsigned PredReg,
540 ARMCC::CondCodes Pred, unsigned PredReg,
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| H A D | ARMLoadStoreOptimizer.cpp | 172 ARMCC::CondCodes Pred, unsigned PredReg);
484 ARMCC::CondCodes Pred, in UpdateBaseRegUses()
625 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
824 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
893 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); in MergeOpsUpdate()
1260 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLSMultiple()
1402 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in MergeBaseUpdateLoadStore()
1509 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSDouble()
1667 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in FixInvalidRegPairOp()
1742 ARMCC::CondCodes CurrPred = ARMCC::AL; in LoadStoreMultipleOpti()
[all …]
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| H A D | ThumbRegisterInfo.h | 43 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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| H A D | Thumb2InstrInfo.h | 71 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
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| H A D | ARMInstructionSelector.cpp | 54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
343 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
345 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL}; in getComparePreds()
523 ARMCC::CondCodes Cond, in insertComparison()
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| H A D | ARMBaseInstrInfo.cpp | 180 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); in convertToThreeAddress()
478 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in reverseBranchCondition()
525 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
526 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
1992 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI, in getInstrPredicate()
2001 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in getInstrPredicate()
2024 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2585 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) { in getSwappedCondition()
2604 inline static ARMCC::CondCodes getCmpToAddCondition(ARMCC::CondCodes CC) { in getCmpToAddCondition()
2854 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4> in optimizeCompareInstr()
[all …]
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| H A D | MLxExpansionPass.cpp | 284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
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| H A D | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| H A D | Thumb2InstrInfo.cpp | 71 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
236 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
674 ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI, in getITInstrPredicate()
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| H A D | Thumb2SizeReduction.cpp | 187 bool is2Addr, ARMCC::CondCodes Pred,
334 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
794 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
887 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
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| H A D | ARMBaseRegisterInfo.cpp | 443 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
786 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
787 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
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| H A D | ARMBaseRegisterInfo.h | 188 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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| H A D | ARMConstantIslandPass.cpp | 1418 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in createNewWater()
1679 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm(); in fixupConditionalBr()
1891 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); in optimizeThumb2Branches()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/Utils/ |
| H A D | ARMBaseInfo.h | 31 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
49 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
70 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
232 MSP430CC::CondCodes BranchCode = in analyzeBranch()
233 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in analyzeBranch()
255 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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| H A D | MSP430.h | 23 enum CondCodes { enum
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | Sparc.h | 42 enum CondCodes { enum
96 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
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| H A D | SparcInstrInfo.cpp | 82 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
301 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
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| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 34 enum CondCodes { enum
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/InstPrinter/ |
| H A D | SparcInstPrinter.cpp | 189 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 914 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
926 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 330 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode()
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