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Searched refs:BaseOp (Results 1 – 23 of 23) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp151 MachineOperand *BaseOp; in runOnMachineFunction() local
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) && in runOnMachineFunction()
154 BaseOp->isReg()) { in runOnMachineFunction()
155 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction()
H A DAArch64InstrInfo.h100 bool getMemOperandWithOffset(MachineInstr &MI, MachineOperand *&BaseOp,
104 bool getMemOperandWithOffsetWidth(MachineInstr &MI, MachineOperand *&BaseOp,
H A DAArch64InstrInfo.cpp1883 MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
1887 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
1891 MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
1922 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
1926 BaseOp = &LdSt.getOperand(2); in getMemOperandWithOffsetWidth()
1930 assert((BaseOp->isReg() || BaseOp->isFI()) && in getMemOperandWithOffsetWidth()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h71 bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
75 bool getMemOperandWithOffsetWidth(MachineInstr &LdSt, MachineOperand *&BaseOp,
H A DLanaiInstrInfo.cpp759 MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument
790 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth()
792 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base " in getMemOperandWithOffsetWidth()
798 MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
814 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineScheduler.cpp1487 MachineOperand *BaseOp; member
1491 : SU(su), BaseOp(Op), Offset(ofs) {} in MemOpInfo()
1494 if (BaseOp->getType() != RHS.BaseOp->getType()) in operator <()
1495 return BaseOp->getType() < RHS.BaseOp->getType(); in operator <()
1497 if (BaseOp->isReg()) in operator <()
1501 if (BaseOp->isFI()) { in operator <()
1503 *BaseOp->getParent()->getParent()->getParent(); in operator <()
1509 if (BaseOp->getIndex() != RHS.BaseOp->getIndex()) in operator <()
1510 return StackGrowsDown ? BaseOp->getIndex() > RHS.BaseOp->getIndex() in operator <()
1511 : BaseOp->getIndex() < RHS.BaseOp->getIndex(); in operator <()
[all …]
H A DImplicitNullChecks.cpp363 MachineOperand *BaseOp; in isSuitableMemoryOp() local
365 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) || in isSuitableMemoryOp()
366 !BaseOp->isReg() || BaseOp->getReg() != PointerReg) in isSuitableMemoryOp()
H A DMachineSink.cpp719 MachineOperand *BaseOp; in SinkingPreventsImplicitNullCheck() local
721 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI)) in SinkingPreventsImplicitNullCheck()
724 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
737 MBP.LHS.getReg() == BaseOp->getReg(); in SinkingPreventsImplicitNullCheck()
H A DMachinePipeliner.cpp2660 MachineOperand *BaseOp; in computeDelta() local
2662 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI)) in computeDelta()
2665 if (!BaseOp->isReg()) in computeDelta()
2668 unsigned BaseReg = BaseOp->getReg(); in computeDelta()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp363 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1) in processAddUses() local
366 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR) in processAddUses()
418 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1) in updateAddUses() local
422 BaseOp.setReg(newReg); in updateAddUses()
423 BaseOp.setIsUndef(AddRegOp.isUndef()); in updateAddUses()
424 BaseOp.setImplicit(AddRegOp.isImplicit()); in updateAddUses()
H A DHexagonInstrInfo.h219 bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
H A DHexagonInstrInfo.cpp2897 MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
2900 BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize); in getMemOperandWithOffset()
2901 assert((!BaseOp || BaseOp->isReg()) && in getMemOperandWithOffset()
2904 return BaseOp != nullptr; in getMemOperandWithOffset()
3139 const MachineOperand &BaseOp = MI.getOperand(BasePos); in getBaseAndOffset() local
3140 if (BaseOp.getSubReg() != 0) in getBaseAndOffset()
3142 return &const_cast<MachineOperand&>(BaseOp); in getBaseAndOffset()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td561 field string BaseOp;
570 let BaseOp = name;
576 let BaseOp = name;
592 field string BaseOp;
600 let BaseOp = name;
606 let BaseOp = name;
H A DSIInstrInfo.cpp269 MachineOperand *&BaseOp, in getMemOperandWithOffset() argument
279 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
281 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base " in getMemOperandWithOffset()
313 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
334 BaseOp = AddrReg; in getMemOperandWithOffset()
340 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base " in getMemOperandWithOffset()
352 BaseOp = SBaseReg; in getMemOperandWithOffset()
354 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base " in getMemOperandWithOffset()
366 BaseOp = VAddr; in getMemOperandWithOffset()
369 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr); in getMemOperandWithOffset()
[all …]
H A DSIInstrInfo.h176 bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
H A DR600Instructions.td1751 let RowFields = ["BaseOp"];
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1501 const MachineOperand &BaseOp = MI.getOperand(2); in MergeBaseUpdateLSDouble() local
1502 unsigned Base = BaseOp.getReg(); in MergeBaseUpdateLSDouble()
1530 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble()
1533 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); in MergeBaseUpdateLSDouble()
1535 MIB.addReg(BaseOp.getReg(), RegState::Kill) in MergeBaseUpdateLSDouble()
1635 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local
1636 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1661 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1662 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.h330 bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp,
H A DX86InstrInfo.cpp3222 MachineInstr &MemOp, MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
3231 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); in getMemOperandWithOffset()
3232 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandWithOffset()
3250 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base " in getMemOperandWithOffset()
H A DX86ISelLowering.cpp19828 unsigned BaseOp = 0; in getX86XALUOOp() local
19833 BaseOp = X86ISD::ADD; in getX86XALUOOp()
19837 BaseOp = X86ISD::ADD; in getX86XALUOOp()
19841 BaseOp = X86ISD::SUB; in getX86XALUOOp()
19845 BaseOp = X86ISD::SUB; in getX86XALUOOp()
19849 BaseOp = X86ISD::SMUL; in getX86XALUOOp()
19853 BaseOp = X86ISD::UMUL; in getX86XALUOOp()
19858 if (BaseOp) { in getX86XALUOOp()
19861 Value = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in getX86XALUOOp()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1142 MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset() argument
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTarget.td1503 // let RowFields = BaseOp
1504 // All add instruction predicated/non-predicated will have to set their BaseOp
1507 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1508 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1509 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3226 unsigned BaseOp = 0; in lowerXALUO() local
3233 BaseOp = SystemZISD::SADDO; in lowerXALUO()
3238 BaseOp = SystemZISD::SSUBO; in lowerXALUO()
3243 BaseOp = SystemZISD::UADDO; in lowerXALUO()
3248 BaseOp = SystemZISD::USUBO; in lowerXALUO()
3255 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerXALUO()
3279 unsigned BaseOp = 0; in lowerADDSUBCARRY() local
3286 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
3291 BaseOp = SystemZISD::SUBCARRY; in lowerADDSUBCARRY()
3303 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry); in lowerADDSUBCARRY()