| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 107 case ISD::AssertSext: return "AssertSext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 57 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
191 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
490 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
1516 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; in ExpandIntegerResult()
2208 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, in ExpandIntRes_AssertSext()
2212 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertSext()
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| H A D | LegalizeVectorOps.cpp | 578 : ISD::AssertSext, in PromoteFP_TO_INT()
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| H A D | SelectionDAGBuilder.cpp | 862 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
4937 case ISD::AssertSext: in getUnderlyingArgReg()
8737 AssertOp = ISD::AssertSext; in LowerCallTo()
9223 AssertOp = ISD::AssertSext; in LowerArguments()
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| H A D | SelectionDAGISel.cpp | 2967 case ISD::AssertSext: in SelectCodeCommon()
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| H A D | DAGCombiner.cpp | 1103 case ISD::AssertSext: in PromoteOperand()
1105 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1)); in PromoteOperand()
1544 case ISD::AssertSext: in visit()
9272 N0.getOperand(0).getOpcode() == ISD::AssertSext && in visitAssertExt()
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| H A D | SelectionDAG.cpp | 3306 case ISD::AssertSext: in ComputeNumSignBits()
4910 case ISD::AssertSext: in getNode()
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| H A D | LegalizeDAG.cpp | 2757 LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res, in ExpandNode()
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| /freebsd-12.1/contrib/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 454 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
613 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1329 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 644 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1099 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 1340 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
1346 N->getOpcode() != ISD::AssertSext &&
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3312 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
3363 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 570 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1507 case ISD::AssertSext: in keepsLowBits()
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| H A D | HexagonISelLowering.cpp | 840 if (Op.getOpcode() != ISD::AssertSext) in LowerSETCC()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 536 setTargetDAGCombine(ISD::AssertSext); in AMDGPUTargetLowering()
3986 case ISD::AssertSext: in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 1314 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
2030 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val, in LowerFormalArguments()
2245 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3648 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
5149 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, in LowerCallResult()
14414 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext) in combineSHL()
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| H A D | PPCISelDAGToDAG.cpp | 2699 (Input.getOperand(0).getOpcode() == ISD::AssertSext || in signExtendInputIfNeeded()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1045 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10626 case ISD::AssertSext: { in checkValueWidth()
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