Home
last modified time | relevance | path

Searched refs:reg_val (Results 1 – 25 of 63) sorted by relevance

123

/f-stack/dpdk/drivers/raw/octeontx2_ep/
H A Dotx2_ep_vf.c106 volatile uint64_t reg_val = 0ull; in sdp_vf_setup_global_iq_reg() local
113 reg_val |= SDP_VF_R_IN_CTL_RDSIZE; in sdp_vf_setup_global_iq_reg()
114 reg_val |= SDP_VF_R_IN_CTL_IS_64B; in sdp_vf_setup_global_iq_reg()
115 reg_val |= SDP_VF_R_IN_CTL_ESR; in sdp_vf_setup_global_iq_reg()
124 volatile uint64_t reg_val = 0ull; in sdp_vf_setup_global_oq_reg() local
246 reg_val = 0xffffffff; in sdp_vf_setup_iq_regs()
342 reg_val |= 0x1ull; in sdp_vf_enable_iq()
356 reg_val |= 0x1ull; in sdp_vf_enable_oq()
381 reg_val &= ~0x1ull; in sdp_vf_disable_iq()
392 reg_val &= ~0x1ull; in sdp_vf_disable_oq()
[all …]
/f-stack/dpdk/drivers/net/liquidio/base/
H A Dlio_23xx_vf.c56 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST; in cn23xx_vf_reset_io_queues()
58 reg_val); in cn23xx_vf_reset_io_queues()
119 reg_val = in cn23xx_vf_setup_global_output_regs()
126 reg_val = in cn23xx_vf_setup_global_output_regs()
130 reg_val |= in cn23xx_vf_setup_global_output_regs()
303 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B; in cn23xx_vf_enable_io_queues()
306 reg_val); in cn23xx_vf_enable_io_queues()
314 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB; in cn23xx_vf_enable_io_queues()
317 reg_val); in cn23xx_vf_enable_io_queues()
328 reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB; in cn23xx_vf_enable_io_queues()
[all …]
/f-stack/freebsd/arm/allwinner/
H A Dif_emac.c375 len = reg_val & 0xffff; in emac_rxeof()
508 uint32_t reg_val; in emac_init_locked() local
531 reg_val |= (0xd << 2); in emac_init_locked()
545 reg_val |= EMAC_TX_AB_M; in emac_init_locked()
546 reg_val &= EMAC_TX_TM; in emac_init_locked()
552 reg_val &= EMAC_RX_TM; in emac_init_locked()
590 reg_val |= EMAC_INT_EN; in emac_init_locked()
682 uint32_t reg_val; in emac_stop_locked() local
708 uint32_t reg_val; in emac_intr() local
734 reg_val |= EMAC_INT_EN; in emac_intr()
[all …]
/f-stack/freebsd/arm/ti/
H A Dti_pinmux.c135 uint16_t reg_val; in ti_pinmux_padconf_set_internal() local
159 reg_val, muxmode); in ti_pinmux_padconf_set_internal()
161 ti_pinmux_write_2(sc, padconf->reg_off, reg_val); in ti_pinmux_padconf_set_internal()
215 uint16_t reg_val; in ti_pinmux_padconf_get() local
226 reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off); in ti_pinmux_padconf_get()
230 *state = (reg_val & ti_pinmux_dev->padconf_sate_mask); in ti_pinmux_padconf_get()
257 uint16_t reg_val; in ti_pinmux_padconf_set_gpiomode() local
279 ti_pinmux_write_2(ti_pinmux_sc, padconf->reg_off, reg_val); in ti_pinmux_padconf_set_gpiomode()
302 uint16_t reg_val; in ti_pinmux_padconf_get_gpiomode() local
318 reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off); in ti_pinmux_padconf_get_gpiomode()
[all …]
/f-stack/dpdk/drivers/crypto/caam_jr/
H A Dcaam_jr_hw.c289 uint32_t reg_val = 0; in hw_job_ring_set_coalescing_param() local
301 reg_val |= (irq_coalescing_timer << JR_REG_JRCFG_LO_ICTT_SHIFT); in hw_job_ring_set_coalescing_param()
304 SET_JR_REG_LO(JRCFG, job_ring, reg_val); in hw_job_ring_set_coalescing_param()
314 uint32_t reg_val = 0; in hw_job_ring_enable_coalescing() local
324 reg_val = GET_JR_REG_LO(JRCFG, job_ring); in hw_job_ring_enable_coalescing()
327 reg_val |= JR_REG_JRCFG_LO_ICEN_EN; in hw_job_ring_enable_coalescing()
330 SET_JR_REG_LO(JRCFG, job_ring, reg_val); in hw_job_ring_enable_coalescing()
341 uint32_t reg_val = 0; in hw_job_ring_disable_coalescing() local
352 reg_val = GET_JR_REG_LO(JRCFG, job_ring); in hw_job_ring_disable_coalescing()
355 reg_val &= ~JR_REG_JRCFG_LO_ICEN_EN; in hw_job_ring_disable_coalescing()
[all …]
/f-stack/dpdk/drivers/raw/ntb/
H A Dntb_hw_intel.c49 uint8_t reg_val; in intel_ntb3_check_ppd() local
52 ret = rte_pci_read_config(hw->pci_dev, &reg_val, in intel_ntb3_check_ppd()
53 sizeof(reg_val), XEON_PPD_OFFSET); in intel_ntb3_check_ppd()
60 switch (reg_val & XEON_PPD_CONN_MASK) { in intel_ntb3_check_ppd()
72 if (reg_val & XEON_PPD_DEV_DSD) { in intel_ntb3_check_ppd()
81 if (reg_val & XEON_PPD_SPLIT_BAR_MASK) { in intel_ntb3_check_ppd()
92 uint32_t reg_val; in intel_ntb4_check_ppd() local
97 switch (reg_val & XEON_GEN4_PPD_CONN_MASK) { in intel_ntb4_check_ppd()
107 if (reg_val & XEON_GEN4_PPD_DEV_DSD) { in intel_ntb4_check_ppd()
273 uint16_t reg_val, reg_off; in intel_ntb_get_link_status() local
[all …]
/f-stack/freebsd/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_gpio.c429 u_int32_t reg_val; in ar9300_gpio_set_intr() local
463 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr()
465 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr()
466 OS_REG_WRITE(ah, regs[i], reg_val); in ar9300_gpio_set_intr()
470 field_val = (reg_val >> shifts[i]) & gpio_mask; in ar9300_gpio_set_intr()
481 reg_val &= ~(1 << reg_bit); in ar9300_gpio_set_intr()
484 reg_val |= (1 << reg_bit); in ar9300_gpio_set_intr()
490 reg_val = OS_REG_READ(ah, regs[i]); in ar9300_gpio_set_intr()
492 reg_val |= (1 << reg_bit); in ar9300_gpio_set_intr()
493 OS_REG_WRITE(ah, regs[i], reg_val); in ar9300_gpio_set_intr()
[all …]
H A Dar9300_recv.c283 u_int32_t reg_val = 0; in ar9300_promisc_mode() local
284 reg_val = OS_REG_READ(ah, AR_RX_FILTER); in ar9300_promisc_mode()
286 reg_val |= AR_RX_PROM; in ar9300_promisc_mode()
288 reg_val &= ~AR_RX_PROM; in ar9300_promisc_mode()
290 OS_REG_WRITE(ah, AR_RX_FILTER, reg_val); in ar9300_promisc_mode()
H A Dar9300_reset.c3255 u_int32_t reg_val;
3276 reg_val &= 0xfffffffd;
3281 reg_val &= 0xfffff7ff;
3301 reg_val = ((reg_val & 0xe3ffffff) | (reflo << 26));
3337 reg_val &= 0xfc0fffff;
3340 reg_val &= 0xfdffffff;
3348 reg_val = reg_val | (0x1 << (19 + i)) | ((offs_6_1) << 20);
3356 reg_val = reg_val | ((offs_6_1 - 1) << 20);
3362 reg_val = reg_val | (0x1 << 25);
3370 reg_val = reg_val | (offs_0 << 25);
[all …]
/f-stack/dpdk/drivers/net/ixgbe/
H A Dixgbe_ipsec.c21 IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSRXIDX, reg_val, \
24 IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSRXIDX, reg_val, \
66 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_KEY | index; in ixgbe_crypto_clear_ipsec_tables()
74 reg_val = IPSRXIDX_WRITE | index; in ixgbe_crypto_clear_ipsec_tables()
95 uint32_t reg_val; in ixgbe_crypto_add_sa() local
167 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | in ixgbe_crypto_add_sa()
188 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | in ixgbe_crypto_add_sa()
203 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | in ixgbe_crypto_add_sa()
277 uint32_t reg_val; in ixgbe_crypto_remove_sa() local
331 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_IP | in ixgbe_crypto_remove_sa()
[all …]
/f-stack/dpdk/drivers/net/qede/base/
H A Decore_init_fw_funcs.c690 u32 reg_val, i; in ecore_poll_on_qm_cmd_ready() local
692 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; in ecore_poll_on_qm_cmd_ready()
1500 u32 reg_val; in ecore_set_vxlan_enable() local
1509 reg_val = ecore_rd(p_hwfn, p_ptt, in ecore_set_vxlan_enable()
1534 u32 reg_val; in ecore_set_gre_enable() local
1546 reg_val = ecore_rd(p_hwfn, p_ptt, in ecore_set_gre_enable()
1589 u32 reg_val; in ecore_set_geneve_enable() local
1601 reg_val = ecore_rd(p_hwfn, p_ptt, in ecore_set_geneve_enable()
1634 u32 reg_val, cfg_mask; in ecore_set_vxlan_no_l2_enable() local
1644 reg_val |= cfg_mask; in ecore_set_vxlan_no_l2_enable()
[all …]
/f-stack/dpdk/drivers/net/igc/
H A Digc_ethdev.h261 uint32_t reg_val = IGC_READ_REG(hw, reg); in igc_read_reg_check_set_bits() local
263 bits |= reg_val; in igc_read_reg_check_set_bits()
264 if (bits == reg_val) in igc_read_reg_check_set_bits()
273 uint32_t reg_val = IGC_READ_REG(hw, reg); in igc_read_reg_check_clear_bits() local
275 bits = reg_val & ~bits; in igc_read_reg_check_clear_bits()
276 if (bits == reg_val) in igc_read_reg_check_clear_bits()
H A Digc_ethdev.c1076 uint32_t reg_val; in eth_igc_start() local
1078 reg_val = IGC_READ_REG(hw, IGC_CTRL); in eth_igc_start()
1079 reg_val &= ~IGC_CTRL_SPEED_MASK; in eth_igc_start()
1082 IGC_WRITE_REG(hw, IGC_CTRL, reg_val); in eth_igc_start()
2455 uint32_t reg_val; in igc_vlan_hw_filter_enable() local
2459 reg_val = IGC_READ_REG(hw, IGC_RCTL); in igc_vlan_hw_filter_enable()
2460 reg_val &= ~IGC_RCTL_CFIEN; in igc_vlan_hw_filter_enable()
2461 reg_val |= IGC_RCTL_VFE; in igc_vlan_hw_filter_enable()
2462 IGC_WRITE_REG(hw, IGC_RCTL, reg_val); in igc_vlan_hw_filter_enable()
2587 uint32_t reg_val; in eth_igc_vlan_tpid_set() local
[all …]
/f-stack/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_x550.c2124 u32 reg_val; in ixgbe_setup_kr_speed_x550em() local
2604 u16 reg_slice, reg_val; in ixgbe_setup_mac_link_sfp_x550em() local
2632 reg_val); in ixgbe_setup_mac_link_sfp_x550em()
2648 u32 reg_val; in ixgbe_setup_sfi_x550a() local
2677 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_sfi_x550a()
2800 u32 reg_val; in ixgbe_setup_ixfi_x550em_x() local
2811 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_ixfi_x550em_x()
2826 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); in ixgbe_setup_ixfi_x550em_x()
2871 u32 reg_val; in ixgbe_setup_ixfi_x550em() local
3029 u32 reg_val; in ixgbe_setup_phy_loopback_x550em() local
[all …]
H A Dixgbe_82599.h33 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
34 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
H A Dixgbe_vf.c220 u32 reg_val; in ixgbe_stop_adapter_vf() local
241 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i)); in ixgbe_stop_adapter_vf()
242 reg_val &= ~IXGBE_RXDCTL_ENABLE; in ixgbe_stop_adapter_vf()
243 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); in ixgbe_stop_adapter_vf()
/f-stack/dpdk/drivers/net/axgbe/
H A Daxgbe_common.h1444 SET_BITS(reg_val, \
1447 AXGMAC_IOWRITE((_pdata), _reg, reg_val); \
1470 SET_BITS(reg_val, \
1495 SET_BITS(reg_val, \
1556 SET_BITS(reg_val, \
1559 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1577 SET_BITS(reg_val, \
1601 SET_BITS(reg_val, \
1635 SET_BITS(reg_val, \
1638 XP_IOWRITE((_pdata), (_reg), reg_val); \
[all …]
H A Daxgbe_dev.c88 unsigned int reg_val = 0; in axgbe_set_ext_mii_mode() local
94 reg_val |= (1 << port); in axgbe_set_ext_mii_mode()
225 unsigned int reg, reg_val; in axgbe_disable_tx_flow_control() local
238 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_disable_tx_flow_control()
240 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_disable_tx_flow_control()
251 unsigned int reg, reg_val; in axgbe_enable_tx_flow_control() local
274 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_enable_tx_flow_control()
281 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_enable_tx_flow_control()
956 unsigned int i, j, reg, reg_val; in axgbe_config_queue_mapping() local
980 reg_val = 0; in axgbe_config_queue_mapping()
[all …]
/f-stack/dpdk/drivers/net/bnx2x/
H A Decore_init.h712 uint32_t reg_val; in ecore_set_mcp_parity() local
715 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
718 reg_val |= mcp_attn_ctl_regs[i].bits; in ecore_set_mcp_parity()
720 reg_val &= ~mcp_attn_ctl_regs[i].bits; in ecore_set_mcp_parity()
722 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
764 uint32_t reg_val, mcp_aeu_bits = in ecore_clear_blocks_parity() local
780 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
782 if (reg_val & reg_mask) in ecore_clear_blocks_parity()
785 reg_val & reg_mask); in ecore_clear_blocks_parity()
791 if (reg_val & mcp_aeu_bits) in ecore_clear_blocks_parity()
[all …]
/f-stack/dpdk/drivers/net/i40e/base/
H A Di40e_diag.c124 u16 reg_val; in i40e_diag_eeprom_test() local
127 ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val); in i40e_diag_eeprom_test()
129 ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) == in i40e_diag_eeprom_test()
H A Di40e_prototype.h77 u32 *reg_val);
79 u32 reg_val);
99 u32 reg_addr, u64 reg_val,
102 u32 reg_addr, u64 *reg_val,
562 u32 reg_addr, u32 *reg_val,
566 u32 reg_addr, u32 reg_val,
568 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
573 u32 reg_addr, u32 reg_val,
579 u32 reg_addr, u32 *reg_val,
/f-stack/freebsd/arm/mv/
H A Dgpio.c887 uint32_t reg_val; in mv_gpio_reg_set() local
889 reg_val = mv_gpio_reg_read(dev, reg); in mv_gpio_reg_set()
890 reg_val |= GPIO(pin); in mv_gpio_reg_set()
891 mv_gpio_reg_write(dev, reg, reg_val); in mv_gpio_reg_set()
897 uint32_t reg_val; in mv_gpio_reg_clear() local
899 reg_val = mv_gpio_reg_read(dev, reg); in mv_gpio_reg_clear()
900 reg_val &= ~(GPIO(pin)); in mv_gpio_reg_clear()
901 mv_gpio_reg_write(dev, reg, reg_val); in mv_gpio_reg_clear()
943 uint32_t reg, reg_val; in mv_gpio_polarity() local
954 if (reg_val) in mv_gpio_polarity()
[all …]
/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_regs.c143 uint32_t *reg_val = data; in hns3_get_32_bit_regs() local
182 *reg_val++ = rte_le_to_cpu_32(*desc_data++); in hns3_get_32_bit_regs()
200 uint64_t *reg_val = data; in hns3_get_64_bit_regs() local
239 *reg_val++ = rte_le_to_cpu_64(*desc_data++); in hns3_get_64_bit_regs()
/f-stack/dpdk/drivers/net/e1000/base/
H A De1000_i210.c826 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; in e1000_pll_workaround_i210() local
835 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; in e1000_pll_workaround_i210()
836 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); in e1000_pll_workaround_i210()
868 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); in e1000_pll_workaround_i210()
869 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
877 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); in e1000_pll_workaround_i210()
878 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
/f-stack/freebsd/arm/freescale/vybrid/
H A Dvf_i2c.c113 uint32_t reg_val; member
458 return vf610_div_table[nitems(vf610_div_table) - 1].reg_val; in i2c_get_div_val()
464 return vf610_div_table[nitems(vf610_div_table) - 1].reg_val; in i2c_get_div_val()
471 return vf610_div_table[i].reg_val; in i2c_get_div_val()

123