Lines Matching refs:reg_val
88 unsigned int reg_val = 0; in axgbe_set_ext_mii_mode() local
94 reg_val |= (1 << port); in axgbe_set_ext_mii_mode()
101 AXGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in axgbe_set_ext_mii_mode()
225 unsigned int reg, reg_val; in axgbe_disable_tx_flow_control() local
238 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_disable_tx_flow_control()
239 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); in axgbe_disable_tx_flow_control()
240 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_disable_tx_flow_control()
251 unsigned int reg, reg_val; in axgbe_enable_tx_flow_control() local
274 reg_val = AXGMAC_IOREAD(pdata, reg); in axgbe_enable_tx_flow_control()
277 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); in axgbe_enable_tx_flow_control()
279 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); in axgbe_enable_tx_flow_control()
281 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_enable_tx_flow_control()
956 unsigned int i, j, reg, reg_val; in axgbe_config_queue_mapping() local
980 reg_val = 0; in axgbe_config_queue_mapping()
982 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); in axgbe_config_queue_mapping()
988 AXGMAC_IOWRITE(pdata, reg, reg_val); in axgbe_config_queue_mapping()
991 reg_val = 0; in axgbe_config_queue_mapping()