Home
last modified time | relevance | path

Searched refs:value (Results 1 – 25 of 578) sorted by relevance

12345678910>>...24

/dpdk/drivers/common/sfc_efx/base/
H A Def10_mac.c694 &value); in ef10_mac_stats_update()
833 &value); in ef10_mac_stats_update()
835 &value); in ef10_mac_stats_update()
838 &value); in ef10_mac_stats_update()
840 &value); in ef10_mac_stats_update()
843 &value); in ef10_mac_stats_update()
845 &value); in ef10_mac_stats_update()
848 &value); in ef10_mac_stats_update()
850 &value); in ef10_mac_stats_update()
853 &value); in ef10_mac_stats_update()
[all …]
H A Dsiena_mac.c252 efx_qword_t value; in siena_mac_stats_update() local
326 &value); in siena_mac_stats_update()
330 &value); in siena_mac_stats_update()
340 &value); in siena_mac_stats_update()
410 &(value.eq_dword[0])); in siena_mac_stats_update()
412 &(value.eq_dword[1])); in siena_mac_stats_update()
416 &(value.eq_dword[0])); in siena_mac_stats_update()
418 &(value.eq_dword[1])); in siena_mac_stats_update()
422 &(value.eq_dword[0])); in siena_mac_stats_update()
424 &(value.eq_dword[1])); in siena_mac_stats_update()
[all …]
/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_yt.c103 u16 value = 0; in ngbe_init_phy_yt() local
113 value |= YT_BCR_PWDN; in ngbe_init_phy_yt()
118 value |= YT_BCR_PWDN; in ngbe_init_phy_yt()
129 u16 value; in ngbe_setup_phy_link_yt() local
148 value = 0; in ngbe_setup_phy_link_yt()
190 value |= value_r9; in ngbe_setup_phy_link_yt()
195 value |= value_r4; in ngbe_setup_phy_link_yt()
368 u16 value; in ngbe_get_phy_advertised_pause_yt() local
380 u16 value; in ngbe_get_phy_lp_advertised_pause_yt() local
392 u16 value; in ngbe_set_phy_pause_adv_yt() local
[all …]
H A Dngbe_phy_mvl.c53 u16 value = 0; in ngbe_check_phy_mode_mvl() local
79 u16 value = 0; in ngbe_init_phy_mvl() local
125 value |= MVL_CTRL_PWDN; in ngbe_init_phy_mvl()
136 u16 value; in ngbe_setup_phy_link_mvl() local
165 value = 0; in ngbe_setup_phy_link_mvl()
199 value_r4 |= value; in ngbe_setup_phy_link_mvl()
205 value_r9 |= value; in ngbe_setup_phy_link_mvl()
268 u16 value; in ngbe_get_phy_advertised_pause_mvl() local
286 u16 value; in ngbe_get_phy_lp_advertised_pause_mvl() local
304 u16 value; in ngbe_set_phy_pause_adv_mvl() local
[all …]
H A Dngbe_phy_rtl.c41 u16 value = 0; in ngbe_phy_led_ctrl_rtl() local
46 value = 0x205B; in ngbe_phy_led_ctrl_rtl()
53 value &= ~0x73; in ngbe_phy_led_ctrl_rtl()
58 value |= 0x2; in ngbe_phy_led_ctrl_rtl()
66 u16 value = 0; in ngbe_init_phy_rtl() local
141 u16 value = 0; in ngbe_setup_phy_link_rtl() local
158 value = 0; in ngbe_setup_phy_link_rtl()
264 u16 value; in ngbe_get_phy_advertised_pause_rtl() local
275 u16 value; in ngbe_get_phy_lp_advertised_pause_rtl() local
281 value = value & RTL_BMSR_ANC; in ngbe_get_phy_lp_advertised_pause_rtl()
[all …]
/dpdk/lib/eal/include/generic/
H A Drte_io.h198 rte_write8(uint8_t value, volatile void *addr);
298 *(volatile uint8_t *)addr = value; in rte_write8_relaxed()
304 *(volatile uint16_t *)addr = value; in rte_write16_relaxed()
310 *(volatile uint32_t *)addr = value; in rte_write32_relaxed()
316 *(volatile uint64_t *)addr = value; in rte_write64_relaxed()
359 rte_write8_relaxed(value, addr); in rte_write8()
366 rte_write16_relaxed(value, addr); in rte_write16()
373 rte_write32_relaxed(value, addr); in rte_write32()
380 rte_write64_relaxed(value, addr); in rte_write64()
387 rte_write32(value, addr); in rte_write32_wc()
[all …]
/dpdk/drivers/net/bonding/
H A Drte_eth_bond_args.c112 const char *value, void *extra_args) in bond_ethdev_parse_slave_port_kvarg() argument
122 int port_id = parse_port_id(value); in bond_ethdev_parse_slave_port_kvarg()
125 value); in bond_ethdev_parse_slave_port_kvarg()
136 const char *value, void *extra_args) in bond_ethdev_parse_slave_mode_kvarg() argument
147 *mode = strtol(value, &endptr, 10); in bond_ethdev_parse_slave_mode_kvarg()
169 const char *value, void *extra_args) in bond_ethdev_parse_slave_agg_mode_kvarg() argument
179 if (strncmp(value, "stable", 6) == 0) in bond_ethdev_parse_slave_agg_mode_kvarg()
185 if (strncmp(value, "count", 5) == 0) in bond_ethdev_parse_slave_agg_mode_kvarg()
201 const char *value, void *extra_args) in bond_ethdev_parse_socket_id_kvarg() argument
224 const char *value, void *extra_args) in bond_ethdev_parse_primary_slave_port_id_kvarg() argument
[all …]
/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_cppcore.c448 value = rte_cpu_to_le_32(value); in nfp_cpp_area_writel()
449 sz = nfp_cpp_area_write(area, offset, &value, sizeof(value)); in nfp_cpp_area_writel()
472 value = rte_cpu_to_le_64(value); in nfp_cpp_area_writeq()
473 sz = nfp_cpp_area_write(area, offset, &value, sizeof(value)); in nfp_cpp_area_writeq()
497 value = rte_cpu_to_le_32(value); in nfp_cpp_writel()
498 sz = nfp_cpp_write(cpp, cpp_id, address, &value, sizeof(value)); in nfp_cpp_writel()
522 value = rte_cpu_to_le_64(value); in nfp_cpp_writeq()
523 sz = nfp_cpp_write(cpp, cpp_id, address, &value, sizeof(value)); in nfp_cpp_writeq()
628 uint32_t value) in nfp_xpb_writelm() argument
755 value = rte_cpu_to_le_32(value); in nfp_cpp_area_fill()
[all …]
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.c1956 value = value | 0x2000; in txgbe_set_link_to_sfi()
1967 value = (value & ~0x700) | 0x500; in txgbe_set_link_to_sfi()
2025 value = (value & ~0x7) | 0x0; in txgbe_set_link_to_sfi()
2035 value = (value & ~0x11) | 0x11; in txgbe_set_link_to_sfi()
2046 value = (value & ~0x11) | 0x0; in txgbe_set_link_to_sfi()
2050 value = value & ~0x1; in txgbe_set_link_to_sfi()
2065 value = (value & ~0x710) | 0x500; in txgbe_set_link_to_sfi()
2082 value = (value & ~0xFFFF) | 0x7706; in txgbe_set_link_to_sfi()
2086 value = (value & ~0x7) | 0x0; in txgbe_set_link_to_sfi()
2096 value = (value & ~0x7) | 0x4; in txgbe_set_link_to_sfi()
[all …]
/dpdk/lib/eal/arm/include/
H A Drte_pause_64.h130 uint16_t value; in rte_wait_until_equal_16() local
135 __RTE_ARM_LOAD_EXC_16(addr, value, memorder) in rte_wait_until_equal_16()
136 if (value != expected) { in rte_wait_until_equal_16()
141 } while (value != expected); in rte_wait_until_equal_16()
149 uint32_t value; in rte_wait_until_equal_32() local
154 __RTE_ARM_LOAD_EXC_32(addr, value, memorder) in rte_wait_until_equal_32()
155 if (value != expected) { in rte_wait_until_equal_32()
160 } while (value != expected); in rte_wait_until_equal_32()
168 uint64_t value; in rte_wait_until_equal_64() local
174 if (value != expected) { in rte_wait_until_equal_64()
[all …]
H A Drte_io_64.h140 rte_write8(uint8_t value, volatile void *addr) in rte_write8() argument
143 rte_write8_relaxed(value, addr); in rte_write8()
147 rte_write16(uint16_t value, volatile void *addr) in rte_write16() argument
150 rte_write16_relaxed(value, addr); in rte_write16()
154 rte_write32(uint32_t value, volatile void *addr) in rte_write32() argument
157 rte_write32_relaxed(value, addr); in rte_write32()
161 rte_write64(uint64_t value, volatile void *addr) in rte_write64() argument
164 rte_write64_relaxed(value, addr); in rte_write64()
169 rte_write32_wc(uint32_t value, volatile void *addr) in rte_write32_wc() argument
171 rte_write32(value, addr); in rte_write32_wc()
[all …]
/dpdk/app/test/
H A Dtest_cfgfile.c53 const char *value; in _test_cfgfile_sample() local
66 TEST_ASSERT(strcmp("value1", value) == 0, in _test_cfgfile_sample()
67 "key1 unexpected value: %s", value); in _test_cfgfile_sample()
76 TEST_ASSERT(strcmp("value2", value) == 0, in _test_cfgfile_sample()
77 "key2 unexpected value: %s", value); in _test_cfgfile_sample()
80 TEST_ASSERT(strcmp("value3", value) == 0, in _test_cfgfile_sample()
81 "key3 unexpected value: %s", value); in _test_cfgfile_sample()
133 const char *value; in test_cfgfile_realloc_sections() local
208 const char *value; in test_cfgfile_empty_key_value_pair() local
225 TEST_ASSERT(strlen(value) == 0, "key unexpected value: %s", value); in test_cfgfile_empty_key_value_pair()
[all …]
/dpdk/drivers/net/cnxk/
H A Dcnxk_ethdev_devargs.c28 val = atoi(value); in parse_outb_nb_desc()
41 val = atoi(value); in parse_outb_nb_crypto_qs()
58 val = strtoul(value, NULL, 0); in parse_ipsec_in_spi_range()
74 val = strtoul(value, NULL, 0); in parse_ipsec_out_max_sa()
89 val = atoi(value); in parse_flow_max_priority()
106 val = atoi(value); in parse_flow_prealloc_size()
123 val = atoi(value); in parse_reta_size()
148 off = strtol(value, &tok1, 16); in parse_pre_l2_hdr_info()
178 val = atoi(value); in parse_sqb_count()
193 if (strcmp(value, "dsa") == 0) in parse_switch_header_type()
[all …]
/dpdk/
H A Dmeson_options.txt3 option('check_includes', type: 'boolean', value: false, description:
5 option('cpu_instruction_set', type: 'string', value: 'auto',
9 option('disable_drivers', type: 'string', value: '', description:
11 option('disable_libs', type: 'string', value: '', description:
15 option('enable_docs', type: 'boolean', value: false, description:
17 option('enable_drivers', type: 'string', value: '', description:
23 option('examples', type: 'string', value: '', description:
25 option('flexran_sdk', type: 'string', value: '', description:
31 option('kernel_dir', type: 'string', value: '', description:
33 option('machine', type: 'string', value: 'auto', description:
[all …]
/dpdk/lib/eal/x86/include/
H A Drte_io.h22 __rte_x86_movdiri(uint32_t value, volatile void *addr) in __rte_x86_movdiri() argument
28 : "a" (value), "d" (addr)); in __rte_x86_movdiri()
33 rte_write32_wc_relaxed(uint32_t value, volatile void *addr) in rte_write32_wc_relaxed() argument
38 __rte_x86_movdiri(value, addr); in rte_write32_wc_relaxed()
40 rte_write32_relaxed(value, addr); in rte_write32_wc_relaxed()
45 __rte_x86_movdiri(value, addr); in rte_write32_wc_relaxed()
47 rte_write32_relaxed(value, addr); in rte_write32_wc_relaxed()
53 rte_write32_wc(uint32_t value, volatile void *addr) in rte_write32_wc() argument
60 rte_write32_wc_relaxed(value, addr); in rte_write32_wc()
62 rte_write32(value, addr); in rte_write32_wc()
/dpdk/drivers/net/e1000/base/
H A De1000_osdep.h75 #define E1000_PCI_REG_WRITE(reg, value) \ argument
76 rte_write32((rte_cpu_to_le_32(value)), reg)
78 #define E1000_PCI_REG_WRITE_RELAXED(reg, value) \ argument
81 #define E1000_PCI_REG_WRITE16(reg, value) \ argument
82 rte_write16((rte_cpu_to_le_16(value)), reg)
120 #define E1000_WRITE_REG(hw, reg, value) \ argument
132 #define E1000_ACCESS_PANIC(x, hw, reg, value) \ argument
143 #define E1000_WRITE_REG_IO(hw, reg, value) \ argument
144 E1000_WRITE_REG(hw, reg, value)
156 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ argument
[all …]
/dpdk/drivers/net/igc/base/
H A Digc_osdep.h85 #define IGC_PCI_REG_WRITE(reg, value) \ argument
86 rte_write32((rte_cpu_to_le_32(value)), reg)
88 #define IGC_PCI_REG_WRITE_RELAXED(reg, value) \ argument
91 #define IGC_PCI_REG_WRITE16(reg, value) \ argument
92 rte_write16((rte_cpu_to_le_16(value)), reg)
121 #define IGC_WRITE_REG(hw, reg, value) \ argument
132 (value))
144 #define IGC_WRITE_REG_IO(hw, reg, value) \ argument
145 IGC_WRITE_REG(hw, reg, value)
157 #define IGC_WRITE_FLASH_REG(hw, reg, value) \ argument
[all …]
/dpdk/drivers/common/qat/qat_adf/
H A Dadf_transport_access_macros_gen4vf.h13 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ argument
16 l_base = (uint32_t)(value & 0xFFFFFFFF); \
17 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
28 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ argument
31 ADF_RING_CSR_RING_CONFIG_GEN4 + (ring << 2), value)
33 #define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \ argument
36 ADF_RING_CSR_RING_TAIL + ((ring) << 2), (value))
38 #define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \ argument
41 ADF_RING_CSR_RING_HEAD + ((ring) << 2), (value))
43 #define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \ argument
[all …]
H A Dadf_transport_access_macros.h105 ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
106 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
109 l_base = (uint32_t)(value & 0xFFFFFFFF); \
110 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
118 ADF_RING_CSR_RING_HEAD + (ring << 2), value)
121 ADF_RING_CSR_RING_TAIL + (ring << 2), value)
129 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
131 ADF_RING_CSR_INT_COL_EN, value)
132 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ argument
135 ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
[all …]
H A Dadf_transport_access_macros_gen4.h22 #define WRITE_CSR_RING_BASE_GEN4(csr_base_addr, bank, ring, value) \ argument
25 l_base = (uint32_t)(value & 0xFFFFFFFF); \
26 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
37 #define WRITE_CSR_RING_CONFIG_GEN4(csr_base_addr, bank, ring, value) \ argument
40 ADF_RING_CSR_RING_CONFIG_GEN4 + (ring << 2), value)
42 #define WRITE_CSR_RING_TAIL_GEN4(csr_base_addr, bank, ring, value) \ argument
45 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
47 #define WRITE_CSR_RING_HEAD_GEN4(csr_base_addr, bank, ring, value) \ argument
50 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
/dpdk/drivers/common/iavf/
H A Diavf_osdep.h96 writel(uint32_t value, volatile void *addr) in writel() argument
98 rte_write32(rte_cpu_to_le_32(value), addr); in writel()
114 writeq(uint64_t value, volatile void *addr) in writeq() argument
116 rte_write64(rte_cpu_to_le_64(value), addr); in writeq()
119 #define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg)) argument
121 #define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg)) argument
132 #define IAVF_PCI_REG_WRITE(reg, value) writel(value, reg) argument
133 #define IAVF_PCI_REG_WRITE_RELAXED(reg, value) writel_relaxed(value, reg) argument
135 #define IAVF_PCI_REG_WC_WRITE(reg, value) \ argument
136 rte_write32_wc((rte_cpu_to_le_32(value)), reg)
[all …]
/dpdk/drivers/crypto/scheduler/
H A Dscheduler_pmd.c268 const char *value, void *extra_args) in parse_integer_arg() argument
272 *i = atoi(value); in parse_integer_arg()
293 if (value == NULL) in parse_coremask_arg()
298 while (isblank(*value)) in parse_coremask_arg()
299 value++; in parse_coremask_arg()
300 if (value[0] == '0' && ((value[1] == 'x') || (value[1] == 'X'))) in parse_coremask_arg()
301 value += 2; in parse_coremask_arg()
302 i = strlen(value); in parse_coremask_arg()
310 c = value[i]; in parse_coremask_arg()
340 const char *token = value; in parse_corelist_arg()
[all …]
/dpdk/app/test-eventdev/
H A Dparser.c79 parser_read_uint64(uint64_t *value, const char *p) in parser_read_uint64() argument
114 *value = val; in parser_read_uint64()
119 parser_read_int32(int32_t *value, const char *p) in parser_read_int32() argument
132 *value = val; in parser_read_int32()
152 *value = val; in parser_read_uint64_hex()
168 *value = val; in parser_read_uint32()
184 *value = val; in parser_read_uint32_hex()
200 *value = val; in parser_read_uint16()
216 *value = val; in parser_read_uint16_hex()
232 *value = val; in parser_read_uint8()
[all …]
H A Dparser.h33 int parser_read_uint64(uint64_t *value, const char *p);
34 int parser_read_uint32(uint32_t *value, const char *p);
35 int parser_read_uint16(uint16_t *value, const char *p);
36 int parser_read_uint8(uint8_t *value, const char *p);
38 int parser_read_uint64_hex(uint64_t *value, const char *p);
39 int parser_read_uint32_hex(uint32_t *value, const char *p);
40 int parser_read_uint16_hex(uint16_t *value, const char *p);
41 int parser_read_uint8_hex(uint8_t *value, const char *p);
43 int parser_read_int32(int32_t *value, const char *p);
/dpdk/drivers/bus/ifpga/
H A Difpga_common.c33 const char *value, void *extra_args) in rte_ifpga_get_string_arg() argument
35 if (!value || !extra_args) in rte_ifpga_get_string_arg()
38 *(char **)extra_args = strdup(value); in rte_ifpga_get_string_arg()
46 const char *value, void *extra_args) in rte_ifpga_get_integer32_arg() argument
48 if (!value || !extra_args) in rte_ifpga_get_integer32_arg()
51 *(int *)extra_args = strtoull(value, NULL, 0); in rte_ifpga_get_integer32_arg()
56 const char *value, void *extra_args) in ifpga_get_integer64_arg() argument
58 if (!value || !extra_args) in ifpga_get_integer64_arg()
61 *(uint64_t *)extra_args = strtoull(value, NULL, 0); in ifpga_get_integer64_arg()

12345678910>>...24