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Searched refs:tc_num (Results 1 – 25 of 26) sorted by relevance

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/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_dcb.c18 txgbe_dcb_pfc_enable(struct txgbe_hw *hw, uint8_t tc_num) in txgbe_dcb_pfc_enable() argument
36 if (!hw->fc.high_water[tc_num] || in txgbe_dcb_pfc_enable()
37 !hw->fc.low_water[tc_num]) { in txgbe_dcb_pfc_enable()
43 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { in txgbe_dcb_pfc_enable()
121 hw->fc.high_water[tc_num]) { in txgbe_dcb_pfc_enable()
122 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[tc_num]) | in txgbe_dcb_pfc_enable()
124 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[tc_num]) | in txgbe_dcb_pfc_enable()
134 fcrth = rd32(hw, TXGBE_PBRXSIZE(tc_num)) - 32; in txgbe_dcb_pfc_enable()
136 wr32(hw, TXGBE_FCWTRLO(tc_num), fcrtl); in txgbe_dcb_pfc_enable()
137 wr32(hw, TXGBE_FCWTRHI(tc_num), fcrth); in txgbe_dcb_pfc_enable()
H A Dtxgbe_dcb.h96 int txgbe_dcb_pfc_enable(struct txgbe_hw *hw, u8 tc_num);
/dpdk/drivers/net/ice/
H A Dice_dcf_sched.c603 cfg->tc_num); in ice_dcf_validate_tc_bw()
612 cfg->tc_num, committed + rest_peak, port_bw); in ice_dcf_validate_tc_bw()
618 cfg->tc_num); in ice_dcf_validate_tc_bw()
624 cfg->tc_num); in ice_dcf_validate_tc_bw()
630 cfg->tc_num, peak, port_bw); in ice_dcf_validate_tc_bw()
791 tc_bw->cfg[i].tc_num = i; in ice_dcf_hierarchy_commit()
808 vf_bw->cfg[num_elem].tc_num = tm_node->tc; in ice_dcf_hierarchy_commit()
/dpdk/drivers/net/ixgbe/
H A Drte_pmd_ixgbe.c710 uint8_t tc_num, in rte_pmd_ixgbe_set_tc_bw_alloc() argument
729 if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) { in rte_pmd_ixgbe_set_tc_bw_alloc()
751 if (nb_tcs != tc_num) { in rte_pmd_ixgbe_set_tc_bw_alloc()
776 bw_conf->tc_num = nb_tcs; in rte_pmd_ixgbe_set_tc_bw_alloc()
H A Drte_pmd_ixgbe.h405 uint8_t tc_num,
H A Dixgbe_ethdev.c4848 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { in ixgbe_dcb_pfc_enable_generic()
4854 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { in ixgbe_dcb_pfc_enable_generic()
4933 hw->fc.high_water[tc_num]) { in ixgbe_dcb_pfc_enable_generic()
4938 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); in ixgbe_dcb_pfc_enable_generic()
4947 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); in ixgbe_dcb_pfc_enable_generic()
4968 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); in ixgbe_dcb_pfc_enable()
4979 uint8_t tc_num; in ixgbe_priority_flow_ctrl_set() local
4996 tc_num = map[pfc_conf->priority]; in ixgbe_priority_flow_ctrl_set()
5015 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; in ixgbe_priority_flow_ctrl_set()
5016 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; in ixgbe_priority_flow_ctrl_set()
[all …]
H A Dixgbe_ethdev.h404 uint8_t tc_num; /* Number of TCs. */ member
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_niccfg.c1114 int hinic_rss_cfg(void *hwdev, u8 rss_en, u8 tmpl_idx, u8 tc_num, u8 *prio_tc) in hinic_rss_cfg() argument
1121 if (!hwdev || !prio_tc || (tc_num & (tc_num - 1))) { in hinic_rss_cfg()
1123 tc_num); in hinic_rss_cfg()
1132 rss_cfg.rq_priority_number = tc_num ? (u8)ilog2(tc_num) : 0; in hinic_rss_cfg()
H A Dhinic_pmd_niccfg.h886 int hinic_rss_cfg(void *hwdev, u8 rss_en, u8 tmpl_idx, u8 tc_num, u8 *prio_tc);
/dpdk/drivers/net/hns3/
H A Dhns3_rss.c540 uint8_t tc_num) in hns3_set_rss_tc_mode_entry() argument
550 for (i = 0; i < tc_num; i++) { in hns3_set_rss_tc_mode_entry()
H A Dhns3_stats.c425 uint32_t tc_num; in hns3_update_port_rpu_drop_stats() local
435 tc_num = 0; in hns3_update_port_rpu_drop_stats()
436 req->tc_queue_num = rte_cpu_to_le_32(tc_num); in hns3_update_port_rpu_drop_stats()
H A Dhns3_ethdev.c2838 pf->tc_max = cfg.tc_num; in hns3_get_board_configuration()
3154 uint8_t tc_num; in hns3_is_rx_buf_ok() local
3157 tc_num = hns3_get_tc_num(hw); in hns3_is_rx_buf_ok()
3167 shared_buf_tc = tc_num * aligned_mps + aligned_mps; in hns3_is_rx_buf_ok()
3191 if (tc_num <= NEED_RESERVE_TC_NUM) in hns3_is_rx_buf_ok()
3195 if (tc_num) in hns3_is_rx_buf_ok()
3196 hi_thrd = hi_thrd / tc_num; in hns3_is_rx_buf_ok()
3337 uint32_t tc_num = hns3_get_tc_num(hw); in hns3_only_alloc_priv_buff() local
3345 if (tc_num) in hns3_only_alloc_priv_buff()
3346 rx_priv = rx_priv / tc_num; in hns3_only_alloc_priv_buff()
[all …]
H A Dhns3_ethdev.h157 uint8_t tc_num; member
/dpdk/drivers/net/i40e/
H A Drte_pmd_i40e.h669 uint8_t tc_num,
H A Drte_pmd_i40e.c1133 uint8_t tc_num, uint8_t *bw_weight) in rte_pmd_i40e_set_vf_tc_bw_alloc() argument
1165 if (tc_num > I40E_MAX_TRAFFIC_CLASS) { in rte_pmd_i40e_set_vf_tc_bw_alloc()
1176 if (sum != tc_num) { in rte_pmd_i40e_set_vf_tc_bw_alloc()
1184 for (i = 0; i < tc_num; i++) { in rte_pmd_i40e_set_vf_tc_bw_alloc()
/dpdk/drivers/net/axgbe/
H A Daxgbe_ethdev.c1338 uint8_t tc_num; in axgbe_priority_flow_ctrl_set() local
1340 tc_num = pdata->pfc_map[pfc_conf->priority]; in axgbe_priority_flow_ctrl_set()
1351 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, in axgbe_priority_flow_ctrl_set()
1353 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, in axgbe_priority_flow_ctrl_set()
1356 switch (tc_num) { in axgbe_priority_flow_ctrl_set()
/dpdk/drivers/net/ice/base/
H A Dice_sched.c271 return pi->sib_head[parent->tc_num][layer]; in ice_sched_get_first_node()
288 if (pi->root->children[i]->tc_num == tc) in ice_sched_get_tc_node()
349 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node) in ice_free_sched_node()
350 pi->sib_head[node->tc_num][node->tx_sched_layer] = in ice_free_sched_node()
944 new_node->tc_num = tc_node->tc_num; in ice_sched_add_elems()
956 if (!pi->sib_head[tc_node->tc_num][layer]) in ice_sched_add_elems()
957 pi->sib_head[tc_node->tc_num][layer] = new_node; in ice_sched_add_elems()
H A Dice_dcb.c1577 tc_node->tc_num = j; in ice_update_port_tc_tree_cfg()
1593 node->tc_num = j; in ice_update_port_tc_tree_cfg()
H A Dice_type.h874 u8 tc_num; member
/dpdk/drivers/common/iavf/
H A Dvirtchnl.h1400 u8 tc_num; member
1845 u8 tc_num; member
/dpdk/drivers/net/txgbe/
H A Dtxgbe_ethdev.h278 uint8_t tc_num; /* Number of TCs. */ member
H A Dtxgbe_ethdev.c3291 uint8_t tc_num; in txgbe_priority_flow_ctrl_set() local
3306 tc_num = map[pfc_conf->priority]; in txgbe_priority_flow_ctrl_set()
3307 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num)); in txgbe_priority_flow_ctrl_set()
3324 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; in txgbe_priority_flow_ctrl_set()
3325 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; in txgbe_priority_flow_ctrl_set()
3327 err = txgbe_dcb_pfc_enable(hw, tc_num); in txgbe_priority_flow_ctrl_set()
H A Dtxgbe_rxtx.c3545 if (bw_conf->tc_num != nb_tcs) in txgbe_dcb_hw_configure()
3560 if (bw_conf->tc_num != nb_tcs) in txgbe_dcb_hw_configure()
/dpdk/drivers/net/iavf/
H A Diavf_tm.c773 if (tc_cap.tc_num != tm_node->tc) { in iavf_node_capabilities_get()
/dpdk/app/test-pmd/
H A Dcmdline.c12850 uint8_t *tc_num, in vf_tc_min_bw_parse_bw_list() argument
12886 *tc_num = ret; in vf_tc_min_bw_parse_bw_list()
12901 uint8_t tc_num; in cmd_vf_tc_min_bw_parsed() local
12908 ret = vf_tc_min_bw_parse_bw_list(bw, &tc_num, res->bw_list); in cmd_vf_tc_min_bw_parsed()
12914 tc_num, bw); in cmd_vf_tc_min_bw_parsed()
12960 uint8_t tc_num; in cmd_tc_min_bw_parsed() local
12974 ret = vf_tc_min_bw_parse_bw_list(bw, &tc_num, res->bw_list); in cmd_tc_min_bw_parsed()
12979 ret = rte_pmd_ixgbe_set_tc_bw_alloc(res->port_id, tc_num, bw); in cmd_tc_min_bw_parsed()

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