1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
4 */
5
6 #ifndef _TXGBE_ETHDEV_H_
7 #define _TXGBE_ETHDEV_H_
8
9 #include <stdint.h>
10
11 #include "base/txgbe.h"
12 #include "txgbe_ptypes.h"
13 #ifdef RTE_LIB_SECURITY
14 #include "txgbe_ipsec.h"
15 #endif
16 #include <rte_flow.h>
17 #include <rte_flow_driver.h>
18 #include <rte_time.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_core.h>
21 #include <rte_hash.h>
22 #include <rte_hash_crc.h>
23 #include <rte_bus_pci.h>
24 #include <rte_tm_driver.h>
25
26 /* need update link, bit flag */
27 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
28 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
29 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
30 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
31 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
32 #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5)
33
34 /*
35 * Defines that were not part of txgbe_type.h as they are not used by the
36 * FreeBSD driver.
37 */
38 #define TXGBE_VFTA_SIZE 128
39 #define TXGBE_HKEY_MAX_INDEX 10
40 /*Default value of Max Rx Queue*/
41 #define TXGBE_MAX_RX_QUEUE_NUM 128
42 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
43
44 #ifndef NBBY
45 #define NBBY 8 /* number of bits in a byte */
46 #endif
47 #define TXGBE_HWSTRIP_BITMAP_SIZE \
48 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
49
50 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
51
52 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
53
54 #define TXGBE_5TUPLE_MAX_PRI 7
55 #define TXGBE_5TUPLE_MIN_PRI 1
56
57
58 /* The overhead from MTU to max frame size. */
59 #define TXGBE_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN)
60
61 #define TXGBE_RSS_OFFLOAD_ALL ( \
62 RTE_ETH_RSS_IPV4 | \
63 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
64 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
65 RTE_ETH_RSS_IPV6 | \
66 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
67 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
68 RTE_ETH_RSS_IPV6_EX | \
69 RTE_ETH_RSS_IPV6_TCP_EX | \
70 RTE_ETH_RSS_IPV6_UDP_EX)
71
72 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
73 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
74
75 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
76 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
77
78 /*
79 * Information about the fdir mode.
80 */
81 struct txgbe_hw_fdir_mask {
82 uint16_t vlan_tci_mask;
83 uint32_t src_ipv4_mask;
84 uint32_t dst_ipv4_mask;
85 uint16_t src_ipv6_mask;
86 uint16_t dst_ipv6_mask;
87 uint16_t src_port_mask;
88 uint16_t dst_port_mask;
89 uint16_t flex_bytes_mask;
90 uint8_t mac_addr_byte_mask;
91 uint32_t tunnel_id_mask;
92 uint8_t tunnel_type_mask;
93 };
94
95 struct txgbe_fdir_filter {
96 TAILQ_ENTRY(txgbe_fdir_filter) entries;
97 struct txgbe_atr_input input; /* key of fdir filter*/
98 uint32_t fdirflags; /* drop or forward */
99 uint32_t fdirhash; /* hash value for fdir */
100 uint8_t queue; /* assigned rx queue */
101 };
102
103 /* list of fdir filters */
104 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
105
106 struct txgbe_fdir_rule {
107 struct txgbe_hw_fdir_mask mask;
108 struct txgbe_atr_input input; /* key of fdir filter */
109 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
110 bool b_mask; /* If TRUE, mask has meaning. */
111 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
112 uint32_t fdirflags; /* drop or forward */
113 uint32_t soft_id; /* an unique value for this rule */
114 uint8_t queue; /* assigned rx queue */
115 uint8_t flex_bytes_offset;
116 };
117
118 struct txgbe_hw_fdir_info {
119 struct txgbe_hw_fdir_mask mask;
120 uint8_t flex_bytes_offset;
121 uint16_t collision;
122 uint16_t free;
123 uint16_t maxhash;
124 uint8_t maxlen;
125 uint64_t add;
126 uint64_t remove;
127 uint64_t f_add;
128 uint64_t f_remove;
129 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
130 /* store the pointers of the filters, index is the hash value. */
131 struct txgbe_fdir_filter **hash_map;
132 struct rte_hash *hash_handle; /* cuckoo hash handler */
133 bool mask_added; /* If already got mask from consistent filter */
134 };
135
136 struct txgbe_rte_flow_rss_conf {
137 struct rte_flow_action_rss conf; /**< RSS parameters. */
138 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
139 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
140 };
141
142 /* structure for interrupt relative data */
143 struct txgbe_interrupt {
144 uint32_t flags;
145 uint32_t mask_misc;
146 uint32_t mask_misc_orig; /* save mask during delayed handler */
147 uint64_t mask;
148 uint64_t mask_orig; /* save mask during delayed handler */
149 };
150
151 #define TXGBE_NB_STAT_MAPPING 32
152 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
153 #define NB_QMAP_FIELDS_PER_QSM_REG 4
154 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
155 struct txgbe_stat_mappings {
156 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
157 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
158 };
159
160 struct txgbe_vfta {
161 uint32_t vfta[TXGBE_VFTA_SIZE];
162 };
163
164 struct txgbe_hwstrip {
165 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
166 };
167
168 /*
169 * VF data which used by PF host only
170 */
171 #define TXGBE_MAX_VF_MC_ENTRIES 30
172
173 struct txgbe_uta_info {
174 uint8_t uc_filter_type;
175 uint16_t uta_in_use;
176 uint32_t uta_shadow[TXGBE_MAX_UTA];
177 };
178
179 struct txgbe_vf_info {
180 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
181 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
182 uint16_t num_vf_mc_hashes;
183 bool clear_to_send;
184 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
185 uint16_t vlan_count;
186 uint8_t api_version;
187 uint16_t switch_domain_id;
188 uint16_t xcast_mode;
189 uint16_t mac_count;
190 };
191
192 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
193
194 struct txgbe_5tuple_filter_info {
195 uint32_t dst_ip;
196 uint32_t src_ip;
197 uint16_t dst_port;
198 uint16_t src_port;
199 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
200 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
201 * used when more than one filter matches.
202 */
203 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
204 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
205 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
206 src_port_mask:1, /* if mask is 1b, do not compare src port. */
207 proto_mask:1; /* if mask is 1b, do not compare protocol. */
208 };
209
210 /* 5tuple filter structure */
211 struct txgbe_5tuple_filter {
212 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
213 uint16_t index; /* the index of 5tuple filter */
214 struct txgbe_5tuple_filter_info filter_info;
215 uint16_t queue; /* rx queue assigned to */
216 };
217
218 #define TXGBE_5TUPLE_ARRAY_SIZE \
219 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
220 (sizeof(uint32_t) * NBBY))
221
222 struct txgbe_ethertype_filter {
223 uint16_t ethertype;
224 uint32_t etqf;
225 uint32_t etqs;
226 /**
227 * If this filter is added by configuration,
228 * it should not be removed.
229 */
230 bool conf;
231 };
232
233 /*
234 * Structure to store filters' info.
235 */
236 struct txgbe_filter_info {
237 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
238 /* store used ethertype filters*/
239 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
240 /* Bit mask for every used 5tuple filter */
241 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
242 struct txgbe_5tuple_filter_list fivetuple_list;
243 /* store the SYN filter info */
244 uint32_t syn_info;
245 /* store the rss filter info */
246 struct txgbe_rte_flow_rss_conf rss_info;
247 };
248
249 struct txgbe_l2_tn_key {
250 enum rte_eth_tunnel_type l2_tn_type;
251 uint32_t tn_id;
252 };
253
254 struct txgbe_l2_tn_filter {
255 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
256 struct txgbe_l2_tn_key key;
257 uint32_t pool;
258 };
259
260 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
261
262 struct txgbe_l2_tn_info {
263 struct txgbe_l2_tn_filter_list l2_tn_list;
264 struct txgbe_l2_tn_filter **hash_map;
265 struct rte_hash *hash_handle;
266 bool e_tag_en; /* e-tag enabled */
267 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
268 uint16_t e_tag_ether_type; /* ether type for e-tag */
269 };
270
271 struct rte_flow {
272 enum rte_filter_type filter_type;
273 void *rule;
274 };
275
276 /* The configuration of bandwidth */
277 struct txgbe_bw_conf {
278 uint8_t tc_num; /* Number of TCs. */
279 };
280
281 /* Struct to store Traffic Manager shaper profile. */
282 struct txgbe_tm_shaper_profile {
283 TAILQ_ENTRY(txgbe_tm_shaper_profile) node;
284 uint32_t shaper_profile_id;
285 uint32_t reference_count;
286 struct rte_tm_shaper_params profile;
287 };
288
289 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile);
290
291 /* node type of Traffic Manager */
292 enum txgbe_tm_node_type {
293 TXGBE_TM_NODE_TYPE_PORT,
294 TXGBE_TM_NODE_TYPE_TC,
295 TXGBE_TM_NODE_TYPE_QUEUE,
296 TXGBE_TM_NODE_TYPE_MAX,
297 };
298
299 /* Struct to store Traffic Manager node configuration. */
300 struct txgbe_tm_node {
301 TAILQ_ENTRY(txgbe_tm_node) node;
302 uint32_t id;
303 uint32_t priority;
304 uint32_t weight;
305 uint32_t reference_count;
306 uint16_t no;
307 struct txgbe_tm_node *parent;
308 struct txgbe_tm_shaper_profile *shaper_profile;
309 struct rte_tm_node_params params;
310 };
311
312 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node);
313
314 /* The configuration of Traffic Manager */
315 struct txgbe_tm_conf {
316 struct txgbe_shaper_profile_list shaper_profile_list;
317 struct txgbe_tm_node *root; /* root node - port */
318 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */
319 struct txgbe_tm_node_list queue_list; /* node list for all the queues */
320 /**
321 * The number of added TC nodes.
322 * It should be no more than the TC number of this port.
323 */
324 uint32_t nb_tc_node;
325 /**
326 * The number of added queue nodes.
327 * It should be no more than the queue number of this port.
328 */
329 uint32_t nb_queue_node;
330 /**
331 * This flag is used to check if APP can change the TM node
332 * configuration.
333 * When it's true, means the configuration is applied to HW,
334 * APP should not change the configuration.
335 * As we don't support on-the-fly configuration, when starting
336 * the port, APP should call the hierarchy_commit API to set this
337 * flag to true. When stopping the port, this flag should be set
338 * to false.
339 */
340 bool committed;
341 };
342
343 /*
344 * Structure to store private data for each driver instance (for each port).
345 */
346 struct txgbe_adapter {
347 struct txgbe_hw hw;
348 struct txgbe_hw_stats stats;
349 struct txgbe_hw_fdir_info fdir;
350 struct txgbe_interrupt intr;
351 struct txgbe_stat_mappings stat_mappings;
352 struct txgbe_vfta shadow_vfta;
353 struct txgbe_hwstrip hwstrip;
354 struct txgbe_dcb_config dcb_config;
355 struct txgbe_vf_info *vfdata;
356 struct txgbe_uta_info uta_info;
357 struct txgbe_filter_info filter;
358 struct txgbe_l2_tn_info l2_tn;
359 struct txgbe_bw_conf bw_conf;
360 #ifdef RTE_LIB_SECURITY
361 struct txgbe_ipsec ipsec;
362 #endif
363 bool rx_bulk_alloc_allowed;
364 struct rte_timecounter systime_tc;
365 struct rte_timecounter rx_tstamp_tc;
366 struct rte_timecounter tx_tstamp_tc;
367 struct txgbe_tm_conf tm_conf;
368
369 /* For RSS reta table update */
370 uint8_t rss_reta_updated;
371 };
372
373 #define TXGBE_DEV_ADAPTER(dev) \
374 ((struct txgbe_adapter *)(dev)->data->dev_private)
375
376 #define TXGBE_DEV_HW(dev) \
377 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
378
379 #define TXGBE_DEV_STATS(dev) \
380 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
381
382 #define TXGBE_DEV_INTR(dev) \
383 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
384
385 #define TXGBE_DEV_FDIR(dev) \
386 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
387
388 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
389 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
390
391 #define TXGBE_DEV_VFTA(dev) \
392 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
393
394 #define TXGBE_DEV_HWSTRIP(dev) \
395 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
396
397 #define TXGBE_DEV_DCB_CONFIG(dev) \
398 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
399
400 #define TXGBE_DEV_VFDATA(dev) \
401 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
402
403 #define TXGBE_DEV_MR_INFO(dev) \
404 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
405
406 #define TXGBE_DEV_UTA_INFO(dev) \
407 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
408
409 #define TXGBE_DEV_FILTER(dev) \
410 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
411
412 #define TXGBE_DEV_L2_TN(dev) \
413 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
414
415 #define TXGBE_DEV_BW_CONF(dev) \
416 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
417
418 #define TXGBE_DEV_TM_CONF(dev) \
419 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf)
420
421 #define TXGBE_DEV_IPSEC(dev) \
422 (&((struct txgbe_adapter *)(dev)->data->dev_private)->ipsec)
423
424 /*
425 * RX/TX function prototypes
426 */
427 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
428
429 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
430
431 void txgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
432
433 void txgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
434
435 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
436 uint16_t nb_rx_desc, unsigned int socket_id,
437 const struct rte_eth_rxconf *rx_conf,
438 struct rte_mempool *mb_pool);
439
440 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
441 uint16_t nb_tx_desc, unsigned int socket_id,
442 const struct rte_eth_txconf *tx_conf);
443
444 uint32_t txgbe_dev_rx_queue_count(void *rx_queue);
445
446 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
447 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
448
449 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
450
451 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
452
453 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
454
455 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
456 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
457 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
458 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
459
460 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
461
462 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
463
464 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
465
466 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
467
468 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
469 struct rte_eth_rxq_info *qinfo);
470
471 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
472 struct rte_eth_txq_info *qinfo);
473
474 int txgbevf_dev_rx_init(struct rte_eth_dev *dev);
475
476 void txgbevf_dev_tx_init(struct rte_eth_dev *dev);
477
478 void txgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
479
480 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
481 uint16_t nb_pkts);
482
483 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
484 uint16_t nb_pkts);
485
486 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
487 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
488 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
489 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
490
491 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
492 uint16_t nb_pkts);
493
494 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
495 uint16_t nb_pkts);
496
497 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
498 uint16_t nb_pkts);
499
500 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
501 struct rte_eth_rss_conf *rss_conf);
502
503 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
504 struct rte_eth_rss_conf *rss_conf);
505
506 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
507
508 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
509 struct rte_eth_ntuple_filter *filter,
510 bool add);
511 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
512 struct rte_eth_ethertype_filter *filter,
513 bool add);
514 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
515 struct rte_eth_syn_filter *filter,
516 bool add);
517
518 /**
519 * l2 tunnel configuration.
520 */
521 struct txgbe_l2_tunnel_conf {
522 enum rte_eth_tunnel_type l2_tunnel_type;
523 uint16_t ether_type; /* ether type in l2 header */
524 uint32_t tunnel_id; /* port tag id for e-tag */
525 uint16_t vf_id; /* VF id for tag insertion */
526 uint32_t pool; /* destination pool for tag based forwarding */
527 };
528
529 int
530 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
531 struct txgbe_l2_tunnel_conf *l2_tunnel,
532 bool restore);
533 int
534 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
535 struct txgbe_l2_tunnel_conf *l2_tunnel);
536 void txgbe_filterlist_init(void);
537 void txgbe_filterlist_flush(void);
538
539 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
540 uint8_t queue, uint8_t msix_vector);
541
542 /*
543 * Flow director function prototypes
544 */
545 int txgbe_fdir_configure(struct rte_eth_dev *dev);
546 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
547 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
548 uint16_t offset);
549 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
550 struct txgbe_fdir_rule *rule,
551 bool del, bool update);
552
553 void txgbe_configure_pb(struct rte_eth_dev *dev);
554 void txgbe_configure_port(struct rte_eth_dev *dev);
555 void txgbe_configure_dcb(struct rte_eth_dev *dev);
556
557 int
558 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
559 int wait_to_complete);
560 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
561
562 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
563
564 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
565
566 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
567
568 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
569
570 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
571 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
572
573 extern const struct rte_flow_ops txgbe_flow_ops;
574
575 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
576 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
577 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
578 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
579
580 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
581 uint16_t tx_rate, uint64_t q_msk);
582 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
583 void txgbe_tm_conf_init(struct rte_eth_dev *dev);
584 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev);
585 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
586 uint16_t tx_rate);
587 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
588 const struct rte_flow_action_rss *in);
589 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
590 const struct rte_flow_action_rss *with);
591 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
592 struct txgbe_rte_flow_rss_conf *conf, bool add);
593
594 static inline int
txgbe_ethertype_filter_lookup(struct txgbe_filter_info * filter_info,uint16_t ethertype)595 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
596 uint16_t ethertype)
597 {
598 int i;
599
600 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
601 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
602 (filter_info->ethertype_mask & (1 << i)))
603 return i;
604 }
605 return -1;
606 }
607
608 static inline int
txgbe_ethertype_filter_insert(struct txgbe_filter_info * filter_info,struct txgbe_ethertype_filter * ethertype_filter)609 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
610 struct txgbe_ethertype_filter *ethertype_filter)
611 {
612 int i;
613
614 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
615 if (filter_info->ethertype_mask & (1 << i))
616 continue;
617
618 filter_info->ethertype_mask |= 1 << i;
619 filter_info->ethertype_filters[i].ethertype =
620 ethertype_filter->ethertype;
621 filter_info->ethertype_filters[i].etqf =
622 ethertype_filter->etqf;
623 filter_info->ethertype_filters[i].etqs =
624 ethertype_filter->etqs;
625 filter_info->ethertype_filters[i].conf =
626 ethertype_filter->conf;
627 break;
628 }
629 return (i < TXGBE_ETF_ID_MAX ? i : -1);
630 }
631
632 static inline int
txgbe_ethertype_filter_remove(struct txgbe_filter_info * filter_info,uint8_t idx)633 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
634 uint8_t idx)
635 {
636 if (idx >= TXGBE_ETF_ID_MAX)
637 return -1;
638 filter_info->ethertype_mask &= ~(1 << idx);
639 filter_info->ethertype_filters[idx].ethertype = 0;
640 filter_info->ethertype_filters[idx].etqf = 0;
641 filter_info->ethertype_filters[idx].etqs = 0;
642 filter_info->ethertype_filters[idx].etqs = FALSE;
643 return idx;
644 }
645
646 #ifdef RTE_LIB_SECURITY
647 int txgbe_ipsec_ctx_create(struct rte_eth_dev *dev);
648 #endif
649
650 /* High threshold controlling when to start sending XOFF frames. */
651 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
652 /* Low threshold controlling when to start sending XON frames. */
653 #define TXGBE_FC_XON_LOTH 64 /*KB*/
654
655 /* Timer value included in XOFF frames. */
656 #define TXGBE_FC_PAUSE_TIME 0x680
657
658 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
659 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
660 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
661
662 /*
663 * Default values for RX/TX configuration
664 */
665 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
666 #define TXGBE_DEFAULT_RX_PTHRESH 8
667 #define TXGBE_DEFAULT_RX_HTHRESH 8
668 #define TXGBE_DEFAULT_RX_WTHRESH 0
669
670 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
671 #define TXGBE_DEFAULT_TX_PTHRESH 32
672 #define TXGBE_DEFAULT_TX_HTHRESH 0
673 #define TXGBE_DEFAULT_TX_WTHRESH 0
674
675 /* Additional timesync values. */
676 #define NSEC_PER_SEC 1000000000L
677 #define TXGBE_INCVAL_10GB 0xCCCCCC
678 #define TXGBE_INCVAL_1GB 0x800000
679 #define TXGBE_INCVAL_100 0xA00000
680 #define TXGBE_INCVAL_10 0xC7F380
681 #define TXGBE_INCVAL_FPGA 0x800000
682 #define TXGBE_INCVAL_SHIFT_10GB 20
683 #define TXGBE_INCVAL_SHIFT_1GB 18
684 #define TXGBE_INCVAL_SHIFT_100 15
685 #define TXGBE_INCVAL_SHIFT_10 12
686 #define TXGBE_INCVAL_SHIFT_FPGA 17
687
688 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
689
690 /* store statistics names and its offset in stats structure */
691 struct rte_txgbe_xstats_name_off {
692 char name[RTE_ETH_XSTATS_NAME_SIZE];
693 unsigned int offset;
694 };
695
696 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
697 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
698 struct rte_ether_addr *mc_addr_set,
699 uint32_t nb_mc_addr);
700 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
701 struct rte_eth_rss_reta_entry64 *reta_conf,
702 uint16_t reta_size);
703 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
704 struct rte_eth_rss_reta_entry64 *reta_conf,
705 uint16_t reta_size);
706 void txgbe_dev_setup_link_alarm_handler(void *param);
707 void txgbe_read_stats_registers(struct txgbe_hw *hw,
708 struct txgbe_hw_stats *hw_stats);
709
710 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
711 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
712 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
713 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
714 uint16_t queue, bool on);
715 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
716 int mask);
717
718 #endif /* _TXGBE_ETHDEV_H_ */
719