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Searched refs:phy_id (Results 1 – 17 of 17) sorted by relevance

/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy.c120 u16 phy_id = 0; in ngbe_validate_phy_addr() local
128 NGBE_MD_DEV_PMA_PMD, &phy_id); in ngbe_validate_phy_addr()
130 if (phy_id != 0xFFFF && phy_id != 0x0) in ngbe_validate_phy_addr()
133 DEBUGOUT("PHY ID HIGH is 0x%04X", phy_id); in ngbe_validate_phy_addr()
/dpdk/drivers/net/pfe/
H A Dpfe_mod.h36 uint32_t phy_id; /* Link phy ID */ member
H A Dpfe_eth.h32 u32 phy_id; member
H A Dpfe_ethdev.c838 unsigned int ii = 0, phy_id = 0; in pfe_get_gemac_if_proprties() local
869 phy_id = rte_be_to_cpu_32((unsigned int)*addr); in pfe_get_gemac_if_proprties()
870 pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; in pfe_get_gemac_if_proprties()
872 if (pdata->ls1012a_eth_pdata[port].phy_id < 32) in pfe_get_gemac_if_proprties()
873 pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] = in pfe_get_gemac_if_proprties()
/dpdk/drivers/net/e1000/base/
H A De1000_82571.c438 u16 phy_id = 0; in e1000_get_phy_id_82571() local
457 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in e1000_get_phy_id_82571()
461 phy->id = (u32)(phy_id << 16); in e1000_get_phy_id_82571()
463 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in e1000_get_phy_id_82571()
467 phy->id |= (u32)(phy_id); in e1000_get_phy_id_82571()
468 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in e1000_get_phy_id_82571()
H A De1000_phy.c205 u16 phy_id; in e1000_get_phy_id() local
214 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in e1000_get_phy_id()
218 phy->id = (u32)(phy_id << 16); in e1000_get_phy_id()
220 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in e1000_get_phy_id()
224 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000_get_phy_id()
225 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in e1000_get_phy_id()
2974 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) in e1000_get_phy_type_from_id() argument
2978 switch (phy_id) { in e1000_get_phy_type_from_id()
H A De1000_phy.h59 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
H A De1000_ich8lan.c173 u32 phy_id = 0; in e1000_phy_is_accessible_pchlan() local
182 phy_id = (u32)(phy_reg << 16); in e1000_phy_is_accessible_pchlan()
186 phy_id = 0; in e1000_phy_is_accessible_pchlan()
189 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
194 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
196 } else if (phy_id) { in e1000_phy_is_accessible_pchlan()
197 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
H A De1000_82575.c591 u16 phy_id; in e1000_get_phy_id_82575() local
652 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); in e1000_get_phy_id_82575()
655 phy_id, phy->addr); in e1000_get_phy_id_82575()
660 if (phy_id == M88_VENDOR) in e1000_get_phy_id_82575()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_phy.c372 u16 phy_id = 0; in ixgbe_validate_phy_addr() local
379 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); in ixgbe_validate_phy_addr()
381 if (phy_id != 0xFFFF && phy_id != 0x0) in ixgbe_validate_phy_addr()
384 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); in ixgbe_validate_phy_addr()
425 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) in ixgbe_get_phy_type_from_id() argument
431 switch (phy_id) { in ixgbe_get_phy_type_from_id()
H A Dixgbe_phy.h130 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.c155 u16 phy_id = 0; in txgbe_validate_phy_addr() local
160 TXGBE_MD_DEV_PMA_PMD, &phy_id); in txgbe_validate_phy_addr()
162 if (phy_id != 0xFFFF && phy_id != 0x0) in txgbe_validate_phy_addr()
165 DEBUGOUT("PHY ID HIGH is 0x%04X", phy_id); in txgbe_validate_phy_addr()
204 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id) in txgbe_get_phy_type_from_id() argument
208 switch (phy_id) { in txgbe_get_phy_type_from_id()
H A Dtxgbe_phy.h418 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id);
/dpdk/drivers/net/igc/base/
H A Digc_phy.c204 u16 phy_id; in igc_get_phy_id() local
213 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
217 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
219 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
223 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
224 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
3014 enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id) in igc_get_phy_type_from_id() argument
3018 switch (phy_id) { in igc_get_phy_type_from_id()
H A Digc_phy.h59 enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
/dpdk/drivers/net/qede/
H A Dqede_debug.c3149 u8 phy_id; in qed_grc_dump_phy() local
3151 for (phy_id = 0; phy_id < OSAL_ARRAY_SIZE(s_phy_defs); phy_id++) { in qed_grc_dump_phy()
3156 phy_defs = &s_phy_defs[phy_id]; in qed_grc_dump_phy()
/dpdk/drivers/net/i40e/base/
H A Di40e_adminq_cmd.h2102 u8 phy_id[4]; member