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Searched refs:intr (Results 1 – 25 of 65) sorted by relevance

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/dpdk/drivers/net/enic/base/
H A Dvnic_intr.c9 void vnic_intr_free(struct vnic_intr *intr) in vnic_intr_free() argument
11 intr->ctrl = NULL; in vnic_intr_free()
17 intr->index = index; in vnic_intr_alloc()
18 intr->vdev = vdev; in vnic_intr_alloc()
21 if (!intr->ctrl) { in vnic_intr_alloc()
32 vnic_intr_coalescing_timer_set(intr, coalescing_timer); in vnic_intr_init()
33 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); in vnic_intr_init()
35 iowrite32(0, &intr->ctrl->int_credits); in vnic_intr_init()
42 coalescing_timer), &intr->ctrl->coalescing_timer); in vnic_intr_coalescing_timer_set()
45 void vnic_intr_clean(struct vnic_intr *intr) in vnic_intr_clean() argument
[all …]
H A Dvnic_intr.h39 static inline void vnic_intr_unmask(struct vnic_intr *intr) in vnic_intr_unmask() argument
41 iowrite32(0, &intr->ctrl->mask); in vnic_intr_unmask()
44 static inline void vnic_intr_mask(struct vnic_intr *intr) in vnic_intr_mask() argument
46 iowrite32(1, &intr->ctrl->mask); in vnic_intr_mask()
49 static inline int vnic_intr_masked(struct vnic_intr *intr) in vnic_intr_masked() argument
51 return ioread32(&intr->ctrl->mask); in vnic_intr_masked()
69 return ioread32(&intr->ctrl->int_credits); in vnic_intr_credits()
74 unsigned int credits = vnic_intr_credits(intr); in vnic_intr_return_all_credits()
87 void vnic_intr_free(struct vnic_intr *intr);
92 void vnic_intr_coalescing_timer_set(struct vnic_intr *intr,
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H A Dvnic_dev.h132 int vnic_dev_raise_intr(struct vnic_dev *vdev, uint16_t intr);
133 int vnic_dev_notify_set(struct vnic_dev *vdev, uint16_t intr);
137 void *notify_addr, dma_addr_t notify_pa, uint16_t intr);
/dpdk/drivers/net/sfc/
H A Dsfc_intr.c143 struct sfc_intr *intr = &sa->intr; in sfc_intr_start() local
164 if (intr->handler != NULL) { in sfc_intr_start()
242 struct sfc_intr *intr = &sa->intr; in sfc_intr_stop() local
247 if (intr->handler != NULL) { in sfc_intr_stop()
278 struct sfc_intr *intr = &sa->intr; in sfc_intr_configure() local
282 intr->handler = NULL; in sfc_intr_configure()
286 if (!intr->lsc_intr && !intr->rxq_intr) in sfc_intr_configure()
289 switch (intr->type) { in sfc_intr_configure()
320 struct sfc_intr *intr = &sa->intr; in sfc_intr_attach() local
329 intr->type = EFX_INTR_LINE; in sfc_intr_attach()
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/dpdk/drivers/common/cnxk/
H A Droc_nix_inl_dev_irq.c70 uint64_t intr; in nix_inl_sso_hwgrp_irq() local
73 if (intr == 0) in nix_inl_sso_hwgrp_irq()
77 if (intr & BIT(1)) in nix_inl_sso_hwgrp_irq()
80 if (intr & ~BIT(1)) in nix_inl_sso_hwgrp_irq()
92 uint64_t intr; in nix_inl_sso_hws_irq() local
95 if (intr == 0) in nix_inl_sso_hws_irq()
194 if (intr == 0) in nix_inl_nix_q_irq()
244 uint64_t intr; in nix_inl_nix_ras_irq() local
248 if (intr == 0) in nix_inl_nix_ras_irq()
276 uint64_t intr; in nix_inl_nix_err_irq() local
[all …]
H A Droc_npa_irq.c12 uint64_t intr; in npa_err_irq() local
14 intr = plt_read64(lf->base + NPA_LF_ERR_INT); in npa_err_irq()
15 if (intr == 0) in npa_err_irq()
18 plt_err("Err_intr=0x%" PRIx64 "", intr); in npa_err_irq()
60 uint64_t intr; in npa_ras_irq() local
62 intr = plt_read64(lf->base + NPA_LF_RAS); in npa_ras_irq()
63 if (intr == 0) in npa_ras_irq()
66 plt_err("Ras_intr=0x%" PRIx64 "", intr); in npa_ras_irq()
69 plt_write64(intr, lf->base + NPA_LF_RAS); in npa_ras_irq()
144 uint64_t intr; in npa_q_irq() local
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H A Droc_sso_irq.c12 uint64_t intr; in sso_hwgrp_irq() local
14 intr = plt_read64(rsrc->base + SSO_LF_GGRP_INT); in sso_hwgrp_irq()
15 if (intr == 0) in sso_hwgrp_irq()
18 plt_err("GGRP %d GGRP_INT=0x%" PRIx64 "", rsrc->rsrc_id, intr); in sso_hwgrp_irq()
21 plt_write64(intr, rsrc->base + SSO_LF_GGRP_INT); in sso_hwgrp_irq()
46 uint64_t intr; in sso_hws_irq() local
48 intr = plt_read64(rsrc->base + SSOW_LF_GWS_INT); in sso_hws_irq()
49 if (intr == 0) in sso_hws_irq()
52 plt_err("GWS %d GWS_INT=0x%" PRIx64 "", rsrc->rsrc_id, intr); in sso_hws_irq()
55 plt_write64(intr, rsrc->base + SSOW_LF_GWS_INT); in sso_hws_irq()
H A Droc_tim_irq.c12 uint64_t intr; in tim_lf_irq() local
17 intr = plt_read64(base + TIM_LF_NRSPERR_INT); in tim_lf_irq()
18 plt_err("TIM RING %d TIM_LF_NRSPERR_INT=0x%" PRIx64 "", ring, intr); in tim_lf_irq()
19 intr = plt_read64(base + TIM_LF_RAS_INT); in tim_lf_irq()
20 plt_err("TIM RING %d TIM_LF_RAS_INT=0x%" PRIx64 "", ring, intr); in tim_lf_irq()
23 plt_write64(intr, base + TIM_LF_NRSPERR_INT); in tim_lf_irq()
24 plt_write64(intr, base + TIM_LF_RAS_INT); in tim_lf_irq()
H A Droc_dev.c370 uint64_t intr; in roc_vf_pf_mbox_irq() local
375 if (!intr) in roc_vf_pf_mbox_irq()
382 dev->intr.bits[vfpf] |= intr; in roc_vf_pf_mbox_irq()
616 uint64_t intr; in roc_pf_vf_mbox_irq() local
619 if (intr == 0) in roc_pf_vf_mbox_irq()
636 uint64_t intr; in roc_af_pf_mbox_irq() local
825 if (!intr) in roc_pf_vf_flr_irq()
907 if (intr) in clear_rvum_interrupts()
912 if (intr) in clear_rvum_interrupts()
917 if (intr) in clear_rvum_interrupts()
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H A Droc_nix_irq.c67 uint64_t intr; in nix_lf_err_irq() local
69 intr = plt_read64(nix->base + NIX_LF_ERR_INT); in nix_lf_err_irq()
70 if (intr == 0) in nix_lf_err_irq()
76 plt_write64(intr, nix->base + NIX_LF_ERR_INT); in nix_lf_err_irq()
116 uint64_t intr; in nix_lf_ras_irq() local
118 intr = plt_read64(nix->base + NIX_LF_RAS); in nix_lf_ras_irq()
119 if (intr == 0) in nix_lf_ras_irq()
124 plt_write64(intr, nix->base + NIX_LF_RAS); in nix_lf_ras_irq()
255 uint64_t intr; in nix_lf_q_irq() local
258 intr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx)); in nix_lf_q_irq()
[all …]
H A Droc_bphy_irq.c394 struct roc_bphy_intr *intr) in roc_bphy_intr_register() argument
400 if (!roc_bphy_intr_available(irq_chip, intr->irq_num)) in roc_bphy_intr_register()
411 CPU_SET(intr->cpu, &intr_cpuset); in roc_bphy_intr_register()
419 ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num, in roc_bphy_intr_register()
420 intr->intr_handler, intr->isr_data); in roc_bphy_intr_register()
H A Droc_cpt.c46 uint64_t intr; in cpt_lf_misc_irq() local
48 intr = plt_read64(lf->rbase + CPT_LF_MISC_INT); in cpt_lf_misc_irq()
49 if (intr == 0) in cpt_lf_misc_irq()
52 plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf); in cpt_lf_misc_irq()
58 plt_write64(intr, lf->rbase + CPT_LF_MISC_INT); in cpt_lf_misc_irq()
110 uint64_t intr; in cpt_lf_done_irq() local
113 intr = plt_read64(lf->rbase + CPT_LF_DONE); in cpt_lf_done_irq()
114 if (intr == 0) in cpt_lf_done_irq()
120 plt_write64(intr, lf->rbase + CPT_LF_DONE_ACK); in cpt_lf_done_irq()
H A Droc_ree.c426 uint64_t intr; in roc_ree_lf_err_intr_handler() local
430 intr = plt_read64(base + REE_LF_MISC_INT); in roc_ree_lf_err_intr_handler()
431 if (intr == 0) in roc_ree_lf_err_intr_handler()
434 plt_ree_dbg("LF %d MISC_INT: 0x%" PRIx64 "", lf_id, intr); in roc_ree_lf_err_intr_handler()
437 plt_write64(intr, base + REE_LF_MISC_INT); in roc_ree_lf_err_intr_handler()
/dpdk/drivers/dma/dpaa/
H A Ddpaa_qdma.c798 int intr; in dpaa_qdma_dequeue_status() local
805 if (intr) { in dpaa_qdma_dequeue_status()
817 intr = qdma_readl(status + FSL_QDMA_DECBR); in dpaa_qdma_dequeue_status()
821 intr = qdma_readl(status + FSL_QDMA_DEDR); in dpaa_qdma_dequeue_status()
830 fsl_queue->stats.completed += intr; in dpaa_qdma_dequeue_status()
832 return intr; in dpaa_qdma_dequeue_status()
844 int intr; in dpaa_qdma_dequeue() local
851 if (intr) { in dpaa_qdma_dequeue()
867 intr = qdma_readl(status + FSL_QDMA_DEDR); in dpaa_qdma_dequeue()
877 fsl_queue->stats.completed += intr; in dpaa_qdma_dequeue()
[all …]
/dpdk/drivers/crypto/octeontx/
H A Dotx_cryptodev_hw_access.c319 uint64_t intr; in otx_cpt_poll_misc() local
321 intr = otx_cpt_read_vf_misc_intr_status(cptvf); in otx_cpt_poll_misc()
323 if (!intr) in otx_cpt_poll_misc()
327 if (likely(intr & CPT_VF_INTR_MBOX_MASK)) { in otx_cpt_poll_misc()
336 (unsigned int long)intr, cptvf->vfid); in otx_cpt_poll_misc()
341 (unsigned int long)intr, cptvf->vfid); in otx_cpt_poll_misc()
345 "%d", cptvf->dev_name, (unsigned int long)intr, in otx_cpt_poll_misc()
350 "%d", cptvf->dev_name, (unsigned int long)intr, in otx_cpt_poll_misc()
355 "%d", cptvf->dev_name, (unsigned int long)intr, in otx_cpt_poll_misc()
360 "%d", cptvf->dev_name, (unsigned int long)intr, in otx_cpt_poll_misc()
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/dpdk/lib/eal/common/
H A Deal_common_trace_points.c71 lib.eal.intr.register)
73 lib.eal.intr.unregister)
75 lib.eal.intr.enable)
77 lib.eal.intr.disable)
/dpdk/drivers/net/vmxnet3/
H A Dvmxnet3_ethdev.c221 if (hw->intr.lsc_only) { in vmxnet3_enable_all_intrs()
457 hw->intr.type = cfg & 0x3; in vmxnet3_alloc_intr_resources()
475 hw->intr.num_intrs = 2; in vmxnet3_alloc_intr_resources()
476 hw->intr.lsc_only = TRUE; in vmxnet3_alloc_intr_resources()
643 if (hw->intr.num_intrs != in vmxnet3_configure_msix()
646 hw->intr.num_intrs, in vmxnet3_configure_msix()
661 hw->intr.type, hw->intr.mask_mode, hw->intr.num_intrs); in vmxnet3_configure_msix()
800 if (hw->intr.lsc_only) in vmxnet3_setup_driver_shared()
825 if (hw->intr.lsc_only) in vmxnet3_setup_driver_shared()
898 hw->intr.num_intrs = 2; in vmxnet3_dev_start()
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/dpdk/drivers/net/txgbe/
H A Dtxgbe_ethdev_vf.c539 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); in txgbevf_intr_disable() local
550 intr->mask_misc = TXGBE_VFIMS_MASK; in txgbevf_intr_disable()
566 intr->mask_misc = 0; in txgbevf_intr_enable()
922 intr->mask_misc &= ~(1 << vec); in txgbevf_dev_rx_queue_intr_enable()
924 wr32(hw, TXGBE_VFIMC, ~intr->mask_misc); in txgbevf_dev_rx_queue_intr_enable()
942 intr->mask_misc |= (1 << vec); in txgbevf_dev_rx_queue_intr_disable()
944 wr32(hw, TXGBE_VFIMS, intr->mask_misc); in txgbevf_dev_rx_queue_intr_disable()
1287 intr->flags = 0; in txgbevf_dev_interrupt_get_status()
1292 intr->flags |= TXGBE_FLAG_MAILBOX; in txgbevf_dev_interrupt_get_status()
1305 if (intr->flags & TXGBE_FLAG_MAILBOX) { in txgbevf_dev_interrupt_action()
[all …]
H A Dtxgbe_ethdev.c2864 intr->mask |= mask; in txgbe_dev_misc_interrupt_setup()
2889 intr->mask |= mask; in txgbe_dev_rxq_interrupt_setup()
2944 intr->flags = 0; in txgbe_dev_interrupt_get_status()
2954 intr->flags |= TXGBE_FLAG_MAILBOX; in txgbe_dev_interrupt_get_status()
2957 intr->flags |= TXGBE_FLAG_MACSEC; in txgbe_dev_interrupt_get_status()
3022 intr->flags &= ~TXGBE_FLAG_MAILBOX; in txgbe_dev_interrupt_action()
3068 intr->mask_orig = intr->mask; in txgbe_dev_interrupt_action()
3127 intr->flags &= ~TXGBE_FLAG_MACSEC; in txgbe_dev_interrupt_delayed_handler()
3131 intr->mask_misc |= TXGBE_ICRMISC_LSC; in txgbe_dev_interrupt_delayed_handler()
3133 intr->mask = intr->mask_orig; in txgbe_dev_interrupt_delayed_handler()
[all …]
/dpdk/drivers/net/ngbe/
H A Dngbe_ethdev.c270 wr32(hw, NGBE_IENMISC, intr->mask_misc); in ngbe_enable_intr()
927 intr->mask_misc |= NGBE_ICRMISC_GPIO; in ngbe_dev_phy_intr_setup()
2012 intr->mask_misc |= NGBE_ICRMISC_PHY; in ngbe_dev_lsc_interrupt_setup()
2013 intr->mask_misc |= NGBE_ICRMISC_GPIO; in ngbe_dev_lsc_interrupt_setup()
2041 intr->mask |= mask; in ngbe_dev_misc_interrupt_setup()
2042 intr->mask_misc |= NGBE_ICRMISC_GPIO; in ngbe_dev_misc_interrupt_setup()
2066 intr->mask |= mask; in ngbe_dev_rxq_interrupt_setup()
2113 intr->flags = 0; in ngbe_dev_interrupt_get_status()
2120 intr->flags |= NGBE_FLAG_MAILBOX; in ngbe_dev_interrupt_get_status()
2123 intr->flags |= NGBE_FLAG_MACSEC; in ngbe_dev_interrupt_get_status()
[all …]
H A Dngbe_ethdev.h125 struct ngbe_interrupt intr; member
164 struct ngbe_interrupt *intr = &ad->intr; in ngbe_dev_intr() local
166 return intr; in ngbe_dev_intr()
/dpdk/drivers/raw/cnxk_bphy/
H A Dcnxk_bphy_irq.c64 struct roc_bphy_intr intr = { in cnxk_bphy_intr_register() local
79 return roc_bphy_intr_register(irq_chip, &intr); in cnxk_bphy_intr_register()
/dpdk/drivers/net/ixgbe/
H A Dixgbe_ethdev.c824 struct ixgbe_interrupt *intr = in ixgbe_enable_intr() local
2392 struct ixgbe_interrupt *intr = in ixgbe_dev_configure() local
2428 struct ixgbe_interrupt *intr = in ixgbe_dev_phy_intr_setup() local
4501 intr->flags = 0; in ixgbe_dev_interrupt_get_status()
4610 intr->mask_original = intr->mask; in ixgbe_dev_interrupt_action()
4672 intr->mask = intr->mask_original; in ixgbe_dev_interrupt_delayed_handler()
4673 intr->mask_original = 0; in ixgbe_dev_interrupt_delayed_handler()
5244 intr->mask = 0; in ixgbevf_intr_disable()
5765 intr->mask |= (1 << vec); in ixgbevf_dev_rx_queue_intr_enable()
5787 intr->mask &= ~(1 << vec); in ixgbevf_dev_rx_queue_intr_disable()
[all …]
/dpdk/drivers/net/atlantic/
H A Datl_ethdev.h31 (&((struct atl_adapter *)adapter)->intr)
51 struct atl_interrupt intr; member
/dpdk/drivers/net/igc/
H A Digc_ethdev.h232 struct igc_interrupt intr; member
255 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)

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