221 	if (hw->intr.lsc_only) {  in vmxnet3_enable_all_intrs()
226 		for (i = 0; i < hw->intr.num_intrs; i++)  in vmxnet3_enable_all_intrs()
457 	hw->intr.type = cfg & 0x3;  in vmxnet3_alloc_intr_resources()
458 	hw->intr.mask_mode = (cfg >> 2) & 0x3;  in vmxnet3_alloc_intr_resources()
460 	if (hw->intr.type == VMXNET3_IT_AUTO)  in vmxnet3_alloc_intr_resources()
461 		hw->intr.type = VMXNET3_IT_MSIX;  in vmxnet3_alloc_intr_resources()
463 	if (hw->intr.type == VMXNET3_IT_MSIX) {  in vmxnet3_alloc_intr_resources()
469 		hw->intr.num_intrs = nvec;  in vmxnet3_alloc_intr_resources()
475 	hw->intr.num_intrs = 2;  in vmxnet3_alloc_intr_resources()
476 	hw->intr.lsc_only = TRUE;  in vmxnet3_alloc_intr_resources()
477 	PMD_INIT_LOG(INFO, "Enabled MSI-X with %d vectors", hw->intr.num_intrs);  in vmxnet3_alloc_intr_resources()
603 	hw->intr.event_intr_idx = 0;  in vmxnet3_configure_msix()
643 	if (hw->intr.num_intrs !=  in vmxnet3_configure_msix()
646 				hw->intr.num_intrs,  in vmxnet3_configure_msix()
657 	for (i = 0; i < hw->intr.num_intrs; i++)  in vmxnet3_configure_msix()
658 		hw->intr.mod_levels[i] = UPT1_IML_ADAPTIVE;  in vmxnet3_configure_msix()
661 		    hw->intr.type, hw->intr.mask_mode, hw->intr.num_intrs);  in vmxnet3_configure_msix()
800 		if (hw->intr.lsc_only)  in vmxnet3_setup_driver_shared()
825 		if (hw->intr.lsc_only)  in vmxnet3_setup_driver_shared()
837 	devRead->intrConf.autoMask = hw->intr.mask_mode == VMXNET3_IMM_AUTO;  in vmxnet3_setup_driver_shared()
838 	devRead->intrConf.numIntrs = hw->intr.num_intrs;  in vmxnet3_setup_driver_shared()
839 	for (i = 0; i < hw->intr.num_intrs; i++)  in vmxnet3_setup_driver_shared()
840 		devRead->intrConf.modLevels[i] = hw->intr.mod_levels[i];  in vmxnet3_setup_driver_shared()
842 	devRead->intrConf.eventIntrIdx = hw->intr.event_intr_idx;  in vmxnet3_setup_driver_shared()
898 		hw->intr.num_intrs = 2;  in vmxnet3_dev_start()
899 		hw->intr.lsc_only = TRUE;  in vmxnet3_dev_start()