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Searched refs:hw (Results 1 – 25 of 416) sorted by relevance

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/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_api.c40 hw->mac.ops.get_rtrup2tc(hw, map); in ixgbe_dcb_get_rtrup2tc()
232 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), in ixgbe_init_hw()
245 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), in ixgbe_reset_hw()
261 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), in ixgbe_start_hw()
399 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), in ixgbe_get_bus_info()
436 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), in ixgbe_stop_adapter()
476 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), in ixgbe_identify_phy()
497 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), in ixgbe_reset_phy()
564 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), in ixgbe_setup_phy_link()
1038 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), in ixgbe_enable_mc()
[all …]
H A Dixgbe_phy.c504 status = hw->phy.ops.read_reg(hw, in ixgbe_reset_phy_generic()
516 status = hw->phy.ops.read_reg(hw, in ixgbe_reset_phy_generic()
983 status = hw->phy.ops.read_reg(hw, in ixgbe_check_phy_link_tnx()
1281 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_sfp_module_generic()
1582 hw->phy.ops.identify_sfp(hw); in ixgbe_get_supported_phy_sfp_layer_generic()
1601 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_get_supported_phy_sfp_layer_generic()
1603 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_get_supported_phy_sfp_layer_generic()
1616 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_get_supported_phy_sfp_layer_generic()
1660 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_qsfp_module_generic()
1707 hw->phy.ops.read_i2c_eeprom(hw, in ixgbe_identify_qsfp_module_generic()
[all …]
H A Dixgbe_common.c365 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
370 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
373 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
1273 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
1410 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1440 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
2450 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
2466 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
2801 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
3564 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
[all …]
H A Dixgbe_x540.c187 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_X540()
205 hw->mac.ops.release_swfw_sync(hw, swfw_mask); in ixgbe_reset_hw_X540()
236 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_X540()
244 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_X540()
247 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); in ixgbe_reset_hw_X540()
254 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_X540()
258 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_X540()
266 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, in ixgbe_reset_hw_X540()
341 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_init_eeprom_params_X540()
564 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_X540()
[all …]
H A Dixgbe_x550.c86 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); in ixgbe_read_cs4227()
99 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); in ixgbe_write_cs4227()
318 hw->mac.ops.set_lan_id(hw); in ixgbe_identify_phy_x550em()
747 return hw->phy.ops.setup_link(hw); in ixgbe_setup_eee_fw()
2257 hw->mac.ops.set_lan_id(hw); in ixgbe_init_phy_ops_X550em()
2426 status = hw->phy.ops.init(hw); in ixgbe_reset_hw_X550em()
2512 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_X550em()
2519 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_X550em()
3408 hw->eeprom.ops.init_params(hw); in ixgbe_calc_checksum_X550()
3616 hw->phy.ops.identify(hw); in ixgbe_get_supported_physical_layer_X550em()
[all …]
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.c72 hw->phy.media_type = hw->phy.get_media_type(hw); in txgbe_read_phy_if()
363 hw->mac.release_swfw_sync(hw, gssr); in txgbe_read_phy_reg()
549 hw->phy.setup_link(hw); in txgbe_setup_phy_link_speed()
644 err = hw->phy.read_reg(hw, in txgbe_check_phy_link_tnx()
845 err = hw->phy.read_i2c_eeprom(hw, in txgbe_identify_sfp_module()
1046 hw->phy.read_i2c_eeprom(hw, in txgbe_identify_qsfp_module()
1050 hw->phy.read_i2c_eeprom(hw, in txgbe_identify_qsfp_module()
1054 hw->phy.read_i2c_eeprom(hw, in txgbe_identify_qsfp_module()
2328 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); in txgbe_set_phy_temp()
2342 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post); in txgbe_set_phy_temp()
[all …]
H A Dtxgbe_hw.c199 hw->phy.media_type = hw->phy.get_media_type(hw); in txgbe_start_hw()
202 hw->mac.clear_vfta(hw); in txgbe_start_hw()
205 hw->mac.clear_hw_cntrs(hw); in txgbe_start_hw()
273 hw->phy.get_fw_version(hw, &hw->fw_version); in txgbe_init_hw()
677 hw->mac.get_mac_addr(hw, hw->mac.addr); in txgbe_init_rx_addrs()
693 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true); in txgbe_init_rx_addrs()
887 hw->mac.fc_autoneg(hw); in txgbe_fc_enable()
3390 hw->phy.reset(hw); in txgbe_reset_hw()
3440 hw->mac.orig_autoc = hw->mac.autoc_read(hw); in txgbe_reset_hw()
3455 hw->mac.get_mac_addr(hw, hw->mac.perm_addr); in txgbe_reset_hw()
[all …]
/dpdk/drivers/net/ngbe/base/
H A Dngbe_hw.c24 hw->mac.clear_vfta(hw); in ngbe_start_hw()
27 hw->mac.clear_hw_cntrs(hw); in ngbe_start_hw()
30 err = hw->mac.setup_fc(hw); in ngbe_start_hw()
59 status = hw->mac.reset_hw(hw); in ngbe_init_hw()
62 status = hw->mac.start_hw(hw); in ngbe_init_hw()
166 hw->phy.reset_hw(hw); in ngbe_reset_hw_em()
173 hw->mac.clear_hw_cntrs(hw); in ngbe_reset_hw_em()
178 hw->mac.get_mac_addr(hw, hw->mac.perm_addr); in ngbe_reset_hw_em()
185 hw->mac.init_rx_addrs(hw); in ngbe_reset_hw_em()
565 hw->mac.get_mac_addr(hw, hw->mac.addr); in ngbe_init_rx_addrs()
[all …]
H A Dngbe_phy_yt.c112 hw->phy.read_reg(hw, YT_BCR, 0, &value); in ngbe_init_phy_yt()
114 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_init_phy_yt()
159 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
165 hw->phy.read_reg(hw, YT_ANA, 0, &value); in ngbe_setup_phy_link_yt()
168 hw->phy.write_reg(hw, YT_ANA, 0, value); in ngbe_setup_phy_link_yt()
194 hw->phy.read_reg(hw, YT_ANA, 0, &value); in ngbe_setup_phy_link_yt()
196 hw->phy.write_reg(hw, YT_ANA, 0, value); in ngbe_setup_phy_link_yt()
199 hw->phy.read_reg(hw, YT_BCR, 0, &value); in ngbe_setup_phy_link_yt()
201 hw->phy.write_reg(hw, YT_BCR, 0, value); in ngbe_setup_phy_link_yt()
225 hw->phy.read_reg(hw, YT_BCR, 0, &value); in ngbe_setup_phy_link_yt()
[all …]
H A Dngbe_phy.c127 hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH, in ngbe_validate_phy_addr()
149 err = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH, in ngbe_get_phy_id()
154 err = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_LOW, in ngbe_get_phy_id()
216 if (hw->mac.check_overtemp(hw) == NGBE_ERR_OVERTEMP) in ngbe_reset_phy()
297 if (hw->mac.acquire_swfw_sync(hw, gssr)) in ngbe_read_phy_reg()
300 err = hw->phy.read_reg_unlocked(hw, reg_addr, device_type, in ngbe_read_phy_reg()
303 hw->mac.release_swfw_sync(hw, gssr); in ngbe_read_phy_reg()
357 if (hw->mac.acquire_swfw_sync(hw, gssr)) in ngbe_write_phy_reg()
360 err = hw->phy.write_reg_unlocked(hw, reg_addr, device_type, in ngbe_write_phy_reg()
363 hw->mac.release_swfw_sync(hw, gssr); in ngbe_write_phy_reg()
[all …]
/dpdk/drivers/net/e1000/base/
H A De1000_api.c19 ret_val = hw->mac.ops.init_params(hw); in e1000_init_mac_params()
45 ret_val = hw->nvm.ops.init_params(hw); in e1000_init_nvm_params()
71 ret_val = hw->phy.ops.init_params(hw); in e1000_init_phy_params()
530 hw->mac.ops.clear_vfta(hw); in e1000_clear_vfta()
647 return hw->mac.ops.init_hw(hw); in e1000_init_hw()
758 return hw->mac.ops.led_on(hw); in e1000_led_on()
991 hw->phy.ops.release(hw); in e1000_release_phy()
1093 return hw->phy.ops.reset(hw); in e1000_phy_hw_reset()
1259 hw->nvm.ops.reload(hw); in e1000_reload_nvm()
1324 hw->phy.ops.power_up(hw); in e1000_power_up_phy()
[all …]
H A De1000_ich8lan.c206 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
210 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
374 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
974 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
1026 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1229 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1433 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1435 hw->phy.ops.reset(hw); in e1000_disable_ulp_lpt_lp()
2114 hw->phy.ops.release(hw); in e1000_update_mc_addr_list_pch2lan()
2307 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
[all …]
H A De1000_82543.c717 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex & in e1000_phy_force_speed_duplex_82543()
768 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_polarity_reversal_workaround_82543()
772 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); in e1000_polarity_reversal_workaround_82543()
856 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_phy_hw_reset_82543()
906 hw->nvm.ops.reload(hw); in e1000_reset_hw_82543()
1001 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); in e1000_setup_link_82543()
1044 ret_val = hw->phy.ops.reset(hw); in e1000_setup_copper_link_82543()
1092 hw->mac.ops.config_collision_dist(hw); in e1000_setup_copper_link_82543()
1126 hw->mac.ops.config_collision_dist(hw); in e1000_setup_fiber_link_82543()
1224 hw->mac.ops.config_collision_dist(hw); in e1000_check_for_copper_link_82543()
[all …]
H A De1000_80003es2lan.c239 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_80003es2lan()
657 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
666 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
696 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
714 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
773 hw->phy.ops.cfg_on_link_up(hw); in e1000_get_link_up_info_80003es2lan()
1073 ret_val = hw->phy.ops.commit(hw); in e1000_copper_link_setup_gg82563_80003es2lan()
1117 if (!hw->mac.ops.check_mng_mode(hw)) { in e1000_copper_link_setup_gg82563_80003es2lan()
1120 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1442 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_80003es2lan()
[all …]
H A De1000_82571.c87 switch (hw->mac.type) { in e1000_init_phy_params_82571()
145 switch (hw->mac.type) { in e1000_init_phy_params_82571()
200 switch (hw->mac.type) { in e1000_init_nvm_params_82571()
232 switch (hw->mac.type) { in e1000_init_nvm_params_82571()
337 switch (hw->mac.type) { in e1000_init_mac_params_82571()
1435 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); in e1000_check_mng_mode_82574()
1487 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, in e1000_check_phy_82574()
1492 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, in e1000_check_phy_82574()
1792 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_82571()
1855 hw->mac.ops.rar_set(hw, hw->mac.addr, in e1000_set_laa_state_82571()
[all …]
H A De1000_mac.c352 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in e1000_init_rx_addrs_generic()
357 hw->mac.ops.rar_set(hw, mac_addr, i); in e1000_init_rx_addrs_generic()
416 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in e1000_check_alt_mac_addr_generic()
436 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in e1000_check_alt_mac_addr_generic()
937 ret_val = hw->nvm.ops.read(hw, in e1000_set_default_fc_generic()
942 ret_val = hw->nvm.ops.read(hw, in e1000_set_default_fc_generic()
983 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_generic()
998 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_generic()
1004 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_generic()
1160 hw->mac.ops.config_collision_dist(hw); in e1000_setup_fiber_serdes_link_generic()
[all …]
H A De1000_82575.c410 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_82575()
535 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_sgmii_82575()
541 hw->phy.ops.release(hw); in e1000_read_phy_reg_sgmii_82575()
568 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_sgmii_82575()
574 hw->phy.ops.release(hw); in e1000_write_phy_reg_sgmii_82575()
714 ret_val = hw->phy.ops.commit(hw); in e1000_phy_hw_reset_sgmii_82575()
1492 ret_val = hw->phy.ops.reset(hw); in e1000_setup_copper_link_82575()
2193 ret_val = hw->phy.ops.acquire(hw); in e1000_read_phy_reg_82580()
2199 hw->phy.ops.release(hw); in e1000_read_phy_reg_82580()
2219 ret_val = hw->phy.ops.acquire(hw); in e1000_write_phy_reg_82580()
[all …]
/dpdk/drivers/net/igc/base/
H A Digc_api.c1011 hw->mac.ops.clear_vfta(hw); in igc_clear_vfta()
1128 return hw->mac.ops.init_hw(hw); in igc_init_hw()
1239 return hw->mac.ops.led_on(hw); in igc_led_on()
1254 return hw->mac.ops.led_off(hw); in igc_led_off()
1472 hw->phy.ops.release(hw); in igc_release_phy()
1574 return hw->phy.ops.reset(hw); in igc_phy_hw_reset()
1589 return hw->phy.ops.commit(hw); in igc_phy_commit()
1725 return hw->nvm.ops.update(hw); in igc_update_nvm_checksum()
1740 hw->nvm.ops.reload(hw); in igc_reload_nvm()
1805 hw->phy.ops.power_up(hw); in igc_power_up_phy()
[all …]
H A Digc_mac.c350 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs_generic()
355 hw->mac.ops.rar_set(hw, mac_addr, i); in igc_init_rx_addrs_generic()
434 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in igc_check_alt_mac_addr_generic()
935 ret_val = hw->nvm.ops.read(hw, in igc_set_default_fc_generic()
940 ret_val = hw->nvm.ops.read(hw, in igc_set_default_fc_generic()
980 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) in igc_setup_link_generic()
992 hw->fc.current_mode = hw->fc.requested_mode; in igc_setup_link_generic()
998 ret_val = hw->mac.ops.setup_physical_interface(hw); in igc_setup_link_generic()
1012 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); in igc_setup_link_generic()
1153 hw->mac.ops.config_collision_dist(hw); in igc_setup_fiber_serdes_link_generic()
[all …]
H A Digc_api.h22 s32 igc_set_i2c_bb(struct igc_hw *hw);
27 void igc_i2c_bus_clear(struct igc_hw *hw);
51 void igc_clear_vfta(struct igc_hw *hw);
55 s32 igc_reset_hw(struct igc_hw *hw);
56 s32 igc_init_hw(struct igc_hw *hw);
57 s32 igc_setup_link(struct igc_hw *hw);
65 s32 igc_setup_led(struct igc_hw *hw);
68 s32 igc_blink_led(struct igc_hw *hw);
69 s32 igc_led_on(struct igc_hw *hw);
70 s32 igc_led_off(struct igc_hw *hw);
[all …]
/dpdk/drivers/net/i40e/base/
H A Di40e_adminq.c277 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
284 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
287 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
294 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
297 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
331 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
334 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
344 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
352 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); in i40e_config_arq_regs()
[all …]
/dpdk/drivers/net/ipn3ke/
H A Dipn3ke_ethdev.c159 hw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
161 hw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
163 hw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
169 hw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw, in ipn3ke_hw_cap_init()
232 if (!(*hw->f_mac_read) || !(*hw->f_mac_write)) in ipn3ke_mtu_set()
235 (*hw->f_mac_read)(hw, in ipn3ke_mtu_set()
241 (*hw->f_mac_read)(hw, in ipn3ke_mtu_set()
249 (*hw->f_mac_write)(hw, in ipn3ke_mtu_set()
255 (*hw->f_mac_write)(hw, in ipn3ke_mtu_set()
323 hw->port_num = hw->retimer.port_num; in ipn3ke_hw_init()
[all …]
/dpdk/drivers/common/iavf/
H A Diavf_adminq.c262 wr32(hw, hw->aq.asq.head, 0); in iavf_config_asq_regs()
263 wr32(hw, hw->aq.asq.tail, 0); in iavf_config_asq_regs()
266 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in iavf_config_asq_regs()
291 wr32(hw, hw->aq.arq.head, 0); in iavf_config_arq_regs()
292 wr32(hw, hw->aq.arq.tail, 0); in iavf_config_arq_regs()
295 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in iavf_config_arq_regs()
301 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); in iavf_config_arq_regs()
457 wr32(hw, hw->aq.asq.len, 0); in iavf_shutdown_asq()
458 wr32(hw, hw->aq.asq.bal, 0); in iavf_shutdown_asq()
459 wr32(hw, hw->aq.asq.bah, 0); in iavf_shutdown_asq()
[all …]
/dpdk/drivers/net/fm10k/base/
H A Dfm10k_api.c102 return fm10k_call_func(hw, hw->mac.ops.reset_hw, (hw), in fm10k_reset_hw()
114 return fm10k_call_func(hw, hw->mac.ops.init_hw, (hw), in fm10k_init_hw()
126 return fm10k_call_func(hw, hw->mac.ops.stop_hw, (hw), in fm10k_stop_hw()
139 return fm10k_call_func(hw, hw->mac.ops.start_hw, (hw), in fm10k_start_hw()
151 return fm10k_call_func(hw, hw->mac.ops.get_bus_info, (hw), in fm10k_get_bus_info()
166 return hw->mac.ops.is_slot_appropriate(hw); in fm10k_is_slot_appropriate()
183 return fm10k_call_func(hw, hw->mac.ops.update_vlan, (hw, vid, idx, set), in fm10k_update_vlan()
196 return fm10k_call_func(hw, hw->mac.ops.read_mac_addr, (hw), in fm10k_read_mac_addr()
263 hw->mac.ops.set_dma_mask(hw, dma_mask); in fm10k_set_dma_mask()
279 return fm10k_call_func(hw, hw->mac.ops.get_fault, (hw, type, fault), in fm10k_get_fault()
[all …]
/dpdk/drivers/dma/hisilicon/
H A Dhisi_dmadev.c246 memset(&hw, 0, sizeof(hw)); in hisi_dma_init_gbl()
573 hw->revision, hw->queue_id, in hisi_dma_dump()
575 hw->ridx, hw->cridx, in hisi_dma_dump()
576 hw->sq_head, hw->sq_tail, hw->cq_sq_head, in hisi_dma_dump()
577 hw->cq_head, hw->cqs_completed, hw->cqe_vld, in hisi_dma_dump()
578 hw->submitted, hw->completed, hw->errors, hw->qfulls); in hisi_dma_dump()
595 if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) { in hisi_dma_copy()
606 hw->sq_tail = (hw->sq_tail + 1) & hw->sq_depth_mask; in hisi_dma_copy()
652 hw->cqe_vld = !hw->cqe_vld; in hisi_dma_scan_cq()
674 if (hw->cq_sq_head >= hw->sq_head) in hisi_dma_calc_cpls()
[all …]

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