Searched refs:default_txportconf (Results 1 – 20 of 20) sorted by relevance
242 info->default_txportconf.ring_size = 256; in mlx5_set_default_params()244 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; in mlx5_set_default_params()248 info->default_txportconf.nb_queues = 16; in mlx5_set_default_params()253 info->default_txportconf.ring_size = 2048; in mlx5_set_default_params()257 info->default_txportconf.nb_queues = 8; in mlx5_set_default_params()262 info->default_txportconf.ring_size = 4096; in mlx5_set_default_params()
135 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; in hns3_dev_infos_get()137 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; in hns3_dev_infos_get()139 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; in hns3_dev_infos_get()
439 dev_info->default_txportconf.burst_size = 32; in ionic_dev_info_get()441 dev_info->default_txportconf.nb_queues = 1; in ionic_dev_info_get()443 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; in ionic_dev_info_get()
365 info->default_txportconf = vf_info.default_txportconf; in hn_vf_info_merge()
800 dev_info->default_txportconf.burst_size = ETH_AF_XDP_DFLT_BUSY_BUDGET; in eth_dev_info()802 dev_info->default_txportconf.nb_queues = 1; in eth_dev_info()804 dev_info->default_txportconf.ring_size = ETH_AF_XDP_DFLT_NUM_DESCS; in eth_dev_info()
588 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; in dpaa_eth_dev_info()590 dev_info->default_txportconf.nb_queues = 1; in dpaa_eth_dev_info()591 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; in dpaa_eth_dev_info()
270 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; in dpaa2_dev_info_get()273 dev_info->default_txportconf.nb_queues = 1; in dpaa2_dev_info_get()274 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; in dpaa2_dev_info_get()
1108 dev_info->default_txportconf.nb_queues = 1; in eth_em_infos_get()1109 dev_info->default_txportconf.ring_size = 256; in eth_em_infos_get()
764 info->default_txportconf.burst_size = HINIC_DEFAULT_BURST_SIZE; in hinic_dev_infos_get()766 info->default_txportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES; in hinic_dev_infos_get()768 info->default_txportconf.ring_size = HINIC_DEFAULT_RING_SIZE; in hinic_dev_infos_get()
1801 dev_info->default_txportconf.burst_size = 32; in ngbe_dev_info_get()1803 dev_info->default_txportconf.nb_queues = 1; in ngbe_dev_info_get()1805 dev_info->default_txportconf.ring_size = 256; in ngbe_dev_info_get()
3803 dev_info->default_txportconf.nb_queues = 2; in i40e_dev_info_get()3809 dev_info->default_txportconf.ring_size = 1024; in i40e_dev_info_get()3811 dev_info->default_txportconf.ring_size = 512; in i40e_dev_info_get()3817 dev_info->default_txportconf.nb_queues = 1; in i40e_dev_info_get()3819 dev_info->default_txportconf.ring_size = 256; in i40e_dev_info_get()3824 dev_info->default_txportconf.nb_queues = 1; in i40e_dev_info_get()3827 dev_info->default_txportconf.ring_size = 256; in i40e_dev_info_get()3830 dev_info->default_txportconf.ring_size = 256; in i40e_dev_info_get()3834 dev_info->default_txportconf.burst_size = 32; in i40e_dev_info_get()
497 device_info->default_txportconf = (struct rte_eth_dev_portconf) { in enicpmd_dev_info_get()
2639 dev_info->default_txportconf.burst_size = 32; in txgbe_dev_info_get()2641 dev_info->default_txportconf.nb_queues = 1; in txgbe_dev_info_get()2643 dev_info->default_txportconf.ring_size = 256; in txgbe_dev_info_get()
3807 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST; in ice_dev_info_get()3809 dev_info->default_txportconf.nb_queues = 1; in ice_dev_info_get()3811 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN; in ice_dev_info_get()
1904 struct rte_eth_dev_portconf default_txportconf; member
1132 nb_tx_q = dev_info.default_txportconf.nb_queues; in rte_eth_dev_configure()2002 nb_tx_desc = dev_info.default_txportconf.ring_size; in rte_eth_tx_queue_setup()
3924 dev_info->default_txportconf.burst_size = 32; in ixgbe_dev_info_get()3926 dev_info->default_txportconf.nb_queues = 1; in ixgbe_dev_info_get()3928 dev_info->default_txportconf.ring_size = 256; in ixgbe_dev_info_get()
484 end of it: ``default_rxportconf`` and ``default_txportconf``. Each of these
3405 else if (port->dev_info.default_txportconf.ring_size) in get_tx_ring_size()3406 *ring_size = port->dev_info.default_txportconf.ring_size; in get_tx_ring_size()
2480 dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; in ena_infos_get()