1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
3 */
4
5 #include <rte_string_fns.h>
6 #include <ethdev_pci.h>
7
8 #include <stdio.h>
9 #include <sys/types.h>
10 #include <sys/stat.h>
11 #include <unistd.h>
12
13 #include <rte_tailq.h>
14
15 #include "eal_firmware.h"
16
17 #include "base/ice_sched.h"
18 #include "base/ice_flow.h"
19 #include "base/ice_dcb.h"
20 #include "base/ice_common.h"
21 #include "base/ice_ptp_hw.h"
22
23 #include "rte_pmd_ice.h"
24 #include "ice_ethdev.h"
25 #include "ice_rxtx.h"
26 #include "ice_generic_flow.h"
27
28 /* devargs */
29 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
30 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
31 #define ICE_PROTO_XTR_ARG "proto_xtr"
32 #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask"
33 #define ICE_ONE_PPS_OUT_ARG "pps_out"
34 #define ICE_RX_LOW_LATENCY_ARG "rx_low_latency"
35
36 #define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
37
38 uint64_t ice_timestamp_dynflag;
39 int ice_timestamp_dynfield_offset = -1;
40
41 static const char * const ice_valid_args[] = {
42 ICE_SAFE_MODE_SUPPORT_ARG,
43 ICE_PIPELINE_MODE_SUPPORT_ARG,
44 ICE_PROTO_XTR_ARG,
45 ICE_HW_DEBUG_MASK_ARG,
46 ICE_ONE_PPS_OUT_ARG,
47 ICE_RX_LOW_LATENCY_ARG,
48 NULL
49 };
50
51 #define PPS_OUT_DELAY_NS 1
52
53 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
54 .name = "intel_pmd_dynfield_proto_xtr_metadata",
55 .size = sizeof(uint32_t),
56 .align = __alignof__(uint32_t),
57 .flags = 0,
58 };
59
60 struct proto_xtr_ol_flag {
61 const struct rte_mbuf_dynflag param;
62 uint64_t *ol_flag;
63 bool required;
64 };
65
66 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
67
68 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
69 [PROTO_XTR_VLAN] = {
70 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
71 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
72 [PROTO_XTR_IPV4] = {
73 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
74 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
75 [PROTO_XTR_IPV6] = {
76 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
77 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
78 [PROTO_XTR_IPV6_FLOW] = {
79 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
80 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
81 [PROTO_XTR_TCP] = {
82 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
83 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
84 [PROTO_XTR_IP_OFFSET] = {
85 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
86 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
87 };
88
89 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
90 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
91 #define ICE_MAX_RES_DESC_NUM 1024
92
93 static int ice_dev_configure(struct rte_eth_dev *dev);
94 static int ice_dev_start(struct rte_eth_dev *dev);
95 static int ice_dev_stop(struct rte_eth_dev *dev);
96 static int ice_dev_close(struct rte_eth_dev *dev);
97 static int ice_dev_reset(struct rte_eth_dev *dev);
98 static int ice_dev_info_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static int ice_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
104
105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
109 uint16_t reta_size);
110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
111 struct rte_eth_rss_reta_entry64 *reta_conf,
112 uint16_t reta_size);
113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
116 struct rte_eth_rss_conf *rss_conf);
117 static int ice_promisc_enable(struct rte_eth_dev *dev);
118 static int ice_promisc_disable(struct rte_eth_dev *dev);
119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
122 uint16_t vlan_id,
123 int on);
124 static int ice_macaddr_set(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr);
126 static int ice_macaddr_add(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr,
128 __rte_unused uint32_t index,
129 uint32_t pool);
130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
132 uint16_t queue_id);
133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
134 uint16_t queue_id);
135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
136 size_t fw_size);
137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
138 uint16_t pvid, int on);
139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
140 static int ice_get_eeprom(struct rte_eth_dev *dev,
141 struct rte_dev_eeprom_info *eeprom);
142 static int ice_get_module_info(struct rte_eth_dev *dev,
143 struct rte_eth_dev_module_info *modinfo);
144 static int ice_get_module_eeprom(struct rte_eth_dev *dev,
145 struct rte_dev_eeprom_info *info);
146 static int ice_stats_get(struct rte_eth_dev *dev,
147 struct rte_eth_stats *stats);
148 static int ice_stats_reset(struct rte_eth_dev *dev);
149 static int ice_xstats_get(struct rte_eth_dev *dev,
150 struct rte_eth_xstat *xstats, unsigned int n);
151 static int ice_xstats_get_names(struct rte_eth_dev *dev,
152 struct rte_eth_xstat_name *xstats_names,
153 unsigned int limit);
154 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
155 const struct rte_flow_ops **ops);
156 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
157 struct rte_eth_udp_tunnel *udp_tunnel);
158 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
159 struct rte_eth_udp_tunnel *udp_tunnel);
160 static int ice_timesync_enable(struct rte_eth_dev *dev);
161 static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
162 struct timespec *timestamp,
163 uint32_t flags);
164 static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
165 struct timespec *timestamp);
166 static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
167 static int ice_timesync_read_time(struct rte_eth_dev *dev,
168 struct timespec *timestamp);
169 static int ice_timesync_write_time(struct rte_eth_dev *dev,
170 const struct timespec *timestamp);
171 static int ice_timesync_disable(struct rte_eth_dev *dev);
172
173 static const struct rte_pci_id pci_id_ice_map[] = {
174 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
175 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
176 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
177 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
178 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
179 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
180 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
181 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
182 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
183 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
184 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
185 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
186 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
187 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
188 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
189 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
190 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
191 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
192 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
193 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
194 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
195 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
196 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
197 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
198 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
199 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E824S) },
200 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_BACKPLANE) },
201 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_QSFP) },
202 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SFP) },
203 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_1GBE) },
204 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825X) },
205 { .vendor_id = 0, /* sentinel */ },
206 };
207
208 static const struct eth_dev_ops ice_eth_dev_ops = {
209 .dev_configure = ice_dev_configure,
210 .dev_start = ice_dev_start,
211 .dev_stop = ice_dev_stop,
212 .dev_close = ice_dev_close,
213 .dev_reset = ice_dev_reset,
214 .dev_set_link_up = ice_dev_set_link_up,
215 .dev_set_link_down = ice_dev_set_link_down,
216 .rx_queue_start = ice_rx_queue_start,
217 .rx_queue_stop = ice_rx_queue_stop,
218 .tx_queue_start = ice_tx_queue_start,
219 .tx_queue_stop = ice_tx_queue_stop,
220 .rx_queue_setup = ice_rx_queue_setup,
221 .rx_queue_release = ice_dev_rx_queue_release,
222 .tx_queue_setup = ice_tx_queue_setup,
223 .tx_queue_release = ice_dev_tx_queue_release,
224 .dev_infos_get = ice_dev_info_get,
225 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
226 .link_update = ice_link_update,
227 .mtu_set = ice_mtu_set,
228 .mac_addr_set = ice_macaddr_set,
229 .mac_addr_add = ice_macaddr_add,
230 .mac_addr_remove = ice_macaddr_remove,
231 .vlan_filter_set = ice_vlan_filter_set,
232 .vlan_offload_set = ice_vlan_offload_set,
233 .reta_update = ice_rss_reta_update,
234 .reta_query = ice_rss_reta_query,
235 .rss_hash_update = ice_rss_hash_update,
236 .rss_hash_conf_get = ice_rss_hash_conf_get,
237 .promiscuous_enable = ice_promisc_enable,
238 .promiscuous_disable = ice_promisc_disable,
239 .allmulticast_enable = ice_allmulti_enable,
240 .allmulticast_disable = ice_allmulti_disable,
241 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
242 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
243 .fw_version_get = ice_fw_version_get,
244 .vlan_pvid_set = ice_vlan_pvid_set,
245 .rxq_info_get = ice_rxq_info_get,
246 .txq_info_get = ice_txq_info_get,
247 .rx_burst_mode_get = ice_rx_burst_mode_get,
248 .tx_burst_mode_get = ice_tx_burst_mode_get,
249 .get_eeprom_length = ice_get_eeprom_length,
250 .get_eeprom = ice_get_eeprom,
251 .get_module_info = ice_get_module_info,
252 .get_module_eeprom = ice_get_module_eeprom,
253 .stats_get = ice_stats_get,
254 .stats_reset = ice_stats_reset,
255 .xstats_get = ice_xstats_get,
256 .xstats_get_names = ice_xstats_get_names,
257 .xstats_reset = ice_stats_reset,
258 .flow_ops_get = ice_dev_flow_ops_get,
259 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
260 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
261 .tx_done_cleanup = ice_tx_done_cleanup,
262 .get_monitor_addr = ice_get_monitor_addr,
263 .timesync_enable = ice_timesync_enable,
264 .timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp,
265 .timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp,
266 .timesync_adjust_time = ice_timesync_adjust_time,
267 .timesync_read_time = ice_timesync_read_time,
268 .timesync_write_time = ice_timesync_write_time,
269 .timesync_disable = ice_timesync_disable,
270 };
271
272 /* store statistics names and its offset in stats structure */
273 struct ice_xstats_name_off {
274 char name[RTE_ETH_XSTATS_NAME_SIZE];
275 unsigned int offset;
276 };
277
278 static const struct ice_xstats_name_off ice_stats_strings[] = {
279 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
280 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
281 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
282 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
283 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
284 rx_unknown_protocol)},
285 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
286 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
287 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
288 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
289 };
290
291 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
292 sizeof(ice_stats_strings[0]))
293
294 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
295 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
296 tx_dropped_link_down)},
297 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
298 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
299 illegal_bytes)},
300 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
301 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
302 mac_local_faults)},
303 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
304 mac_remote_faults)},
305 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
306 rx_len_errors)},
307 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
308 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
309 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
310 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
311 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
312 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
313 rx_size_127)},
314 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
315 rx_size_255)},
316 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
317 rx_size_511)},
318 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
319 rx_size_1023)},
320 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
321 rx_size_1522)},
322 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
323 rx_size_big)},
324 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
325 rx_undersize)},
326 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
327 rx_oversize)},
328 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
329 mac_short_pkt_dropped)},
330 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
331 rx_fragments)},
332 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
333 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
334 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
335 tx_size_127)},
336 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
337 tx_size_255)},
338 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
339 tx_size_511)},
340 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
341 tx_size_1023)},
342 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
343 tx_size_1522)},
344 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
345 tx_size_big)},
346 };
347
348 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
349 sizeof(ice_hw_port_strings[0]))
350
351 static void
ice_init_controlq_parameter(struct ice_hw * hw)352 ice_init_controlq_parameter(struct ice_hw *hw)
353 {
354 /* fields for adminq */
355 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
356 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
357 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
358 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
359
360 /* fields for mailboxq, DPDK used as PF host */
361 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
362 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
363 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
364 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
365
366 /* fields for sideband queue */
367 hw->sbq.num_rq_entries = ICE_SBQ_LEN;
368 hw->sbq.num_sq_entries = ICE_SBQ_LEN;
369 hw->sbq.rq_buf_size = ICE_SBQ_MAX_BUF_LEN;
370 hw->sbq.sq_buf_size = ICE_SBQ_MAX_BUF_LEN;
371
372 }
373
374 static int
lookup_proto_xtr_type(const char * xtr_name)375 lookup_proto_xtr_type(const char *xtr_name)
376 {
377 static struct {
378 const char *name;
379 enum proto_xtr_type type;
380 } xtr_type_map[] = {
381 { "vlan", PROTO_XTR_VLAN },
382 { "ipv4", PROTO_XTR_IPV4 },
383 { "ipv6", PROTO_XTR_IPV6 },
384 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
385 { "tcp", PROTO_XTR_TCP },
386 { "ip_offset", PROTO_XTR_IP_OFFSET },
387 };
388 uint32_t i;
389
390 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
391 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
392 return xtr_type_map[i].type;
393 }
394
395 return -1;
396 }
397
398 /*
399 * Parse elem, the elem could be single number/range or '(' ')' group
400 * 1) A single number elem, it's just a simple digit. e.g. 9
401 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
402 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
403 * Within group elem, '-' used for a range separator;
404 * ',' used for a single number.
405 */
406 static int
parse_queue_set(const char * input,int xtr_type,struct ice_devargs * devargs)407 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
408 {
409 const char *str = input;
410 char *end = NULL;
411 uint32_t min, max;
412 uint32_t idx;
413
414 while (isblank(*str))
415 str++;
416
417 if (!isdigit(*str) && *str != '(')
418 return -1;
419
420 /* process single number or single range of number */
421 if (*str != '(') {
422 errno = 0;
423 idx = strtoul(str, &end, 10);
424 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
425 return -1;
426
427 while (isblank(*end))
428 end++;
429
430 min = idx;
431 max = idx;
432
433 /* process single <number>-<number> */
434 if (*end == '-') {
435 end++;
436 while (isblank(*end))
437 end++;
438 if (!isdigit(*end))
439 return -1;
440
441 errno = 0;
442 idx = strtoul(end, &end, 10);
443 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
444 return -1;
445
446 max = idx;
447 while (isblank(*end))
448 end++;
449 }
450
451 if (*end != ':')
452 return -1;
453
454 for (idx = RTE_MIN(min, max);
455 idx <= RTE_MAX(min, max); idx++)
456 devargs->proto_xtr[idx] = xtr_type;
457
458 return 0;
459 }
460
461 /* process set within bracket */
462 str++;
463 while (isblank(*str))
464 str++;
465 if (*str == '\0')
466 return -1;
467
468 min = ICE_MAX_QUEUE_NUM;
469 do {
470 /* go ahead to the first digit */
471 while (isblank(*str))
472 str++;
473 if (!isdigit(*str))
474 return -1;
475
476 /* get the digit value */
477 errno = 0;
478 idx = strtoul(str, &end, 10);
479 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
480 return -1;
481
482 /* go ahead to separator '-',',' and ')' */
483 while (isblank(*end))
484 end++;
485 if (*end == '-') {
486 if (min == ICE_MAX_QUEUE_NUM)
487 min = idx;
488 else /* avoid continuous '-' */
489 return -1;
490 } else if (*end == ',' || *end == ')') {
491 max = idx;
492 if (min == ICE_MAX_QUEUE_NUM)
493 min = idx;
494
495 for (idx = RTE_MIN(min, max);
496 idx <= RTE_MAX(min, max); idx++)
497 devargs->proto_xtr[idx] = xtr_type;
498
499 min = ICE_MAX_QUEUE_NUM;
500 } else {
501 return -1;
502 }
503
504 str = end + 1;
505 } while (*end != ')' && *end != '\0');
506
507 return 0;
508 }
509
510 static int
parse_queue_proto_xtr(const char * queues,struct ice_devargs * devargs)511 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
512 {
513 const char *queue_start;
514 uint32_t idx;
515 int xtr_type;
516 char xtr_name[32];
517
518 while (isblank(*queues))
519 queues++;
520
521 if (*queues != '[') {
522 xtr_type = lookup_proto_xtr_type(queues);
523 if (xtr_type < 0)
524 return -1;
525
526 devargs->proto_xtr_dflt = xtr_type;
527
528 return 0;
529 }
530
531 queues++;
532 do {
533 while (isblank(*queues))
534 queues++;
535 if (*queues == '\0')
536 return -1;
537
538 queue_start = queues;
539
540 /* go across a complete bracket */
541 if (*queue_start == '(') {
542 queues += strcspn(queues, ")");
543 if (*queues != ')')
544 return -1;
545 }
546
547 /* scan the separator ':' */
548 queues += strcspn(queues, ":");
549 if (*queues++ != ':')
550 return -1;
551 while (isblank(*queues))
552 queues++;
553
554 for (idx = 0; ; idx++) {
555 if (isblank(queues[idx]) ||
556 queues[idx] == ',' ||
557 queues[idx] == ']' ||
558 queues[idx] == '\0')
559 break;
560
561 if (idx > sizeof(xtr_name) - 2)
562 return -1;
563
564 xtr_name[idx] = queues[idx];
565 }
566 xtr_name[idx] = '\0';
567 xtr_type = lookup_proto_xtr_type(xtr_name);
568 if (xtr_type < 0)
569 return -1;
570
571 queues += idx;
572
573 while (isblank(*queues) || *queues == ',' || *queues == ']')
574 queues++;
575
576 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
577 return -1;
578 } while (*queues != '\0');
579
580 return 0;
581 }
582
583 static int
handle_proto_xtr_arg(__rte_unused const char * key,const char * value,void * extra_args)584 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
585 void *extra_args)
586 {
587 struct ice_devargs *devargs = extra_args;
588
589 if (value == NULL || extra_args == NULL)
590 return -EINVAL;
591
592 if (parse_queue_proto_xtr(value, devargs) < 0) {
593 PMD_DRV_LOG(ERR,
594 "The protocol extraction parameter is wrong : '%s'",
595 value);
596 return -1;
597 }
598
599 return 0;
600 }
601
602 static void
ice_check_proto_xtr_support(struct ice_hw * hw)603 ice_check_proto_xtr_support(struct ice_hw *hw)
604 {
605 #define FLX_REG(val, fld, idx) \
606 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
607 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
608 static struct {
609 uint32_t rxdid;
610 uint8_t opcode;
611 uint8_t protid_0;
612 uint8_t protid_1;
613 } xtr_sets[] = {
614 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
615 ICE_RX_OPC_EXTRACT,
616 ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
617 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
618 ICE_RX_OPC_EXTRACT,
619 ICE_PROT_IPV4_OF_OR_S,
620 ICE_PROT_IPV4_OF_OR_S },
621 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
622 ICE_RX_OPC_EXTRACT,
623 ICE_PROT_IPV6_OF_OR_S,
624 ICE_PROT_IPV6_OF_OR_S },
625 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
626 ICE_RX_OPC_EXTRACT,
627 ICE_PROT_IPV6_OF_OR_S,
628 ICE_PROT_IPV6_OF_OR_S },
629 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
630 ICE_RX_OPC_EXTRACT,
631 ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
632 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
633 ICE_RX_OPC_PROTID,
634 ICE_PROT_IPV4_OF_OR_S,
635 ICE_PROT_IPV6_OF_OR_S },
636 };
637 uint32_t i;
638
639 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
640 uint32_t rxdid = xtr_sets[i].rxdid;
641 uint32_t v;
642
643 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
644 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
645
646 if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
647 FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
648 ice_proto_xtr_hw_support[i] = true;
649 }
650
651 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
652 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
653
654 if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
655 FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
656 ice_proto_xtr_hw_support[i] = true;
657 }
658 }
659 }
660
661 static int
ice_res_pool_init(struct ice_res_pool_info * pool,uint32_t base,uint32_t num)662 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
663 uint32_t num)
664 {
665 struct pool_entry *entry;
666
667 if (!pool || !num)
668 return -EINVAL;
669
670 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
671 if (!entry) {
672 PMD_INIT_LOG(ERR,
673 "Failed to allocate memory for resource pool");
674 return -ENOMEM;
675 }
676
677 /* queue heap initialize */
678 pool->num_free = num;
679 pool->num_alloc = 0;
680 pool->base = base;
681 LIST_INIT(&pool->alloc_list);
682 LIST_INIT(&pool->free_list);
683
684 /* Initialize element */
685 entry->base = 0;
686 entry->len = num;
687
688 LIST_INSERT_HEAD(&pool->free_list, entry, next);
689 return 0;
690 }
691
692 static int
ice_res_pool_alloc(struct ice_res_pool_info * pool,uint16_t num)693 ice_res_pool_alloc(struct ice_res_pool_info *pool,
694 uint16_t num)
695 {
696 struct pool_entry *entry, *valid_entry;
697
698 if (!pool || !num) {
699 PMD_INIT_LOG(ERR, "Invalid parameter");
700 return -EINVAL;
701 }
702
703 if (pool->num_free < num) {
704 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
705 num, pool->num_free);
706 return -ENOMEM;
707 }
708
709 valid_entry = NULL;
710 /* Lookup in free list and find most fit one */
711 LIST_FOREACH(entry, &pool->free_list, next) {
712 if (entry->len >= num) {
713 /* Find best one */
714 if (entry->len == num) {
715 valid_entry = entry;
716 break;
717 }
718 if (!valid_entry ||
719 valid_entry->len > entry->len)
720 valid_entry = entry;
721 }
722 }
723
724 /* Not find one to satisfy the request, return */
725 if (!valid_entry) {
726 PMD_INIT_LOG(ERR, "No valid entry found");
727 return -ENOMEM;
728 }
729 /**
730 * The entry have equal queue number as requested,
731 * remove it from alloc_list.
732 */
733 if (valid_entry->len == num) {
734 LIST_REMOVE(valid_entry, next);
735 } else {
736 /**
737 * The entry have more numbers than requested,
738 * create a new entry for alloc_list and minus its
739 * queue base and number in free_list.
740 */
741 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
742 if (!entry) {
743 PMD_INIT_LOG(ERR,
744 "Failed to allocate memory for "
745 "resource pool");
746 return -ENOMEM;
747 }
748 entry->base = valid_entry->base;
749 entry->len = num;
750 valid_entry->base += num;
751 valid_entry->len -= num;
752 valid_entry = entry;
753 }
754
755 /* Insert it into alloc list, not sorted */
756 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
757
758 pool->num_free -= valid_entry->len;
759 pool->num_alloc += valid_entry->len;
760
761 return valid_entry->base + pool->base;
762 }
763
764 static void
ice_res_pool_destroy(struct ice_res_pool_info * pool)765 ice_res_pool_destroy(struct ice_res_pool_info *pool)
766 {
767 struct pool_entry *entry, *next_entry;
768
769 if (!pool)
770 return;
771
772 for (entry = LIST_FIRST(&pool->alloc_list);
773 entry && (next_entry = LIST_NEXT(entry, next), 1);
774 entry = next_entry) {
775 LIST_REMOVE(entry, next);
776 rte_free(entry);
777 }
778
779 for (entry = LIST_FIRST(&pool->free_list);
780 entry && (next_entry = LIST_NEXT(entry, next), 1);
781 entry = next_entry) {
782 LIST_REMOVE(entry, next);
783 rte_free(entry);
784 }
785
786 pool->num_free = 0;
787 pool->num_alloc = 0;
788 pool->base = 0;
789 LIST_INIT(&pool->alloc_list);
790 LIST_INIT(&pool->free_list);
791 }
792
793 static void
ice_vsi_config_default_rss(struct ice_aqc_vsi_props * info)794 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
795 {
796 /* Set VSI LUT selection */
797 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
798 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
799 /* Set Hash scheme */
800 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
801 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
802 /* enable TC */
803 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
804 }
805
806 static enum ice_status
ice_vsi_config_tc_queue_mapping(struct ice_vsi * vsi,struct ice_aqc_vsi_props * info,uint8_t enabled_tcmap)807 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
808 struct ice_aqc_vsi_props *info,
809 uint8_t enabled_tcmap)
810 {
811 uint16_t fls, qp_idx;
812
813 /* default tc 0 now. Multi-TC supporting need to be done later.
814 * Configure TC and queue mapping parameters, for enabled TC,
815 * allocate qpnum_per_tc queues to this traffic.
816 */
817 if (enabled_tcmap != 0x01) {
818 PMD_INIT_LOG(ERR, "only TC0 is supported");
819 return -ENOTSUP;
820 }
821
822 /* vector 0 is reserved and 1 vector for ctrl vsi */
823 if (vsi->adapter->hw.func_caps.common_cap.num_msix_vectors < 2)
824 vsi->nb_qps = 0;
825 else
826 vsi->nb_qps = RTE_MIN
827 ((uint16_t)vsi->adapter->hw.func_caps.common_cap.num_msix_vectors - 2,
828 RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC));
829
830 /* nb_qps(hex) -> fls */
831 /* 0000 -> 0 */
832 /* 0001 -> 0 */
833 /* 0002 -> 1 */
834 /* 0003 ~ 0004 -> 2 */
835 /* 0005 ~ 0008 -> 3 */
836 /* 0009 ~ 0010 -> 4 */
837 /* 0011 ~ 0020 -> 5 */
838 /* 0021 ~ 0040 -> 6 */
839 /* 0041 ~ 0080 -> 7 */
840 /* 0081 ~ 0100 -> 8 */
841 fls = (vsi->nb_qps == 0) ? 0 : rte_fls_u32(vsi->nb_qps - 1);
842
843 qp_idx = 0;
844 /* Set tc and queue mapping with VSI */
845 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
846 ICE_AQ_VSI_TC_Q_OFFSET_S) |
847 (fls << ICE_AQ_VSI_TC_Q_NUM_S));
848
849 /* Associate queue number with VSI */
850 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
851 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
852 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
853 info->valid_sections |=
854 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
855 /* Set the info.ingress_table and info.egress_table
856 * for UP translate table. Now just set it to 1:1 map by default
857 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
858 */
859 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
860 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
861 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
862 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
863 return 0;
864 }
865
866 static int
ice_init_mac_address(struct rte_eth_dev * dev)867 ice_init_mac_address(struct rte_eth_dev *dev)
868 {
869 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
870
871 if (!rte_is_unicast_ether_addr
872 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
873 PMD_INIT_LOG(ERR, "Invalid MAC address");
874 return -EINVAL;
875 }
876
877 rte_ether_addr_copy(
878 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
879 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
880
881 dev->data->mac_addrs =
882 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
883 if (!dev->data->mac_addrs) {
884 PMD_INIT_LOG(ERR,
885 "Failed to allocate memory to store mac address");
886 return -ENOMEM;
887 }
888 /* store it to dev data */
889 rte_ether_addr_copy(
890 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
891 &dev->data->mac_addrs[0]);
892 return 0;
893 }
894
895 /* Find out specific MAC filter */
896 static struct ice_mac_filter *
ice_find_mac_filter(struct ice_vsi * vsi,struct rte_ether_addr * macaddr)897 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
898 {
899 struct ice_mac_filter *f;
900
901 TAILQ_FOREACH(f, &vsi->mac_list, next) {
902 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
903 return f;
904 }
905
906 return NULL;
907 }
908
909 static int
ice_add_mac_filter(struct ice_vsi * vsi,struct rte_ether_addr * mac_addr)910 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
911 {
912 struct ice_fltr_list_entry *m_list_itr = NULL;
913 struct ice_mac_filter *f;
914 struct LIST_HEAD_TYPE list_head;
915 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
916 int ret = 0;
917
918 /* If it's added and configured, return */
919 f = ice_find_mac_filter(vsi, mac_addr);
920 if (f) {
921 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
922 return 0;
923 }
924
925 INIT_LIST_HEAD(&list_head);
926
927 m_list_itr = (struct ice_fltr_list_entry *)
928 ice_malloc(hw, sizeof(*m_list_itr));
929 if (!m_list_itr) {
930 ret = -ENOMEM;
931 goto DONE;
932 }
933 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
934 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
935 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
936 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
937 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
938 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
939 m_list_itr->fltr_info.vsi_handle = vsi->idx;
940
941 LIST_ADD(&m_list_itr->list_entry, &list_head);
942
943 /* Add the mac */
944 ret = ice_add_mac(hw, &list_head);
945 if (ret != ICE_SUCCESS) {
946 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
947 ret = -EINVAL;
948 goto DONE;
949 }
950 /* Add the mac addr into mac list */
951 f = rte_zmalloc(NULL, sizeof(*f), 0);
952 if (!f) {
953 PMD_DRV_LOG(ERR, "failed to allocate memory");
954 ret = -ENOMEM;
955 goto DONE;
956 }
957 rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
958 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
959 vsi->mac_num++;
960
961 ret = 0;
962
963 DONE:
964 rte_free(m_list_itr);
965 return ret;
966 }
967
968 static int
ice_remove_mac_filter(struct ice_vsi * vsi,struct rte_ether_addr * mac_addr)969 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
970 {
971 struct ice_fltr_list_entry *m_list_itr = NULL;
972 struct ice_mac_filter *f;
973 struct LIST_HEAD_TYPE list_head;
974 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
975 int ret = 0;
976
977 /* Can't find it, return an error */
978 f = ice_find_mac_filter(vsi, mac_addr);
979 if (!f)
980 return -EINVAL;
981
982 INIT_LIST_HEAD(&list_head);
983
984 m_list_itr = (struct ice_fltr_list_entry *)
985 ice_malloc(hw, sizeof(*m_list_itr));
986 if (!m_list_itr) {
987 ret = -ENOMEM;
988 goto DONE;
989 }
990 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
991 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
992 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
993 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
994 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
995 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
996 m_list_itr->fltr_info.vsi_handle = vsi->idx;
997
998 LIST_ADD(&m_list_itr->list_entry, &list_head);
999
1000 /* remove the mac filter */
1001 ret = ice_remove_mac(hw, &list_head);
1002 if (ret != ICE_SUCCESS) {
1003 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
1004 ret = -EINVAL;
1005 goto DONE;
1006 }
1007
1008 /* Remove the mac addr from mac list */
1009 TAILQ_REMOVE(&vsi->mac_list, f, next);
1010 rte_free(f);
1011 vsi->mac_num--;
1012
1013 ret = 0;
1014 DONE:
1015 rte_free(m_list_itr);
1016 return ret;
1017 }
1018
1019 /* Find out specific VLAN filter */
1020 static struct ice_vlan_filter *
ice_find_vlan_filter(struct ice_vsi * vsi,struct ice_vlan * vlan)1021 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1022 {
1023 struct ice_vlan_filter *f;
1024
1025 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
1026 if (vlan->tpid == f->vlan_info.vlan.tpid &&
1027 vlan->vid == f->vlan_info.vlan.vid)
1028 return f;
1029 }
1030
1031 return NULL;
1032 }
1033
1034 static int
ice_add_vlan_filter(struct ice_vsi * vsi,struct ice_vlan * vlan)1035 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1036 {
1037 struct ice_fltr_list_entry *v_list_itr = NULL;
1038 struct ice_vlan_filter *f;
1039 struct LIST_HEAD_TYPE list_head;
1040 struct ice_hw *hw;
1041 int ret = 0;
1042
1043 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1044 return -EINVAL;
1045
1046 hw = ICE_VSI_TO_HW(vsi);
1047
1048 /* If it's added and configured, return. */
1049 f = ice_find_vlan_filter(vsi, vlan);
1050 if (f) {
1051 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
1052 return 0;
1053 }
1054
1055 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
1056 return 0;
1057
1058 INIT_LIST_HEAD(&list_head);
1059
1060 v_list_itr = (struct ice_fltr_list_entry *)
1061 ice_malloc(hw, sizeof(*v_list_itr));
1062 if (!v_list_itr) {
1063 ret = -ENOMEM;
1064 goto DONE;
1065 }
1066 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1067 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1068 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1069 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1070 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1071 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1072 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1073 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1074
1075 LIST_ADD(&v_list_itr->list_entry, &list_head);
1076
1077 /* Add the vlan */
1078 ret = ice_add_vlan(hw, &list_head);
1079 if (ret != ICE_SUCCESS) {
1080 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1081 ret = -EINVAL;
1082 goto DONE;
1083 }
1084
1085 /* Add vlan into vlan list */
1086 f = rte_zmalloc(NULL, sizeof(*f), 0);
1087 if (!f) {
1088 PMD_DRV_LOG(ERR, "failed to allocate memory");
1089 ret = -ENOMEM;
1090 goto DONE;
1091 }
1092 f->vlan_info.vlan.tpid = vlan->tpid;
1093 f->vlan_info.vlan.vid = vlan->vid;
1094 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1095 vsi->vlan_num++;
1096
1097 ret = 0;
1098
1099 DONE:
1100 rte_free(v_list_itr);
1101 return ret;
1102 }
1103
1104 static int
ice_remove_vlan_filter(struct ice_vsi * vsi,struct ice_vlan * vlan)1105 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1106 {
1107 struct ice_fltr_list_entry *v_list_itr = NULL;
1108 struct ice_vlan_filter *f;
1109 struct LIST_HEAD_TYPE list_head;
1110 struct ice_hw *hw;
1111 int ret = 0;
1112
1113 if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1114 return -EINVAL;
1115
1116 hw = ICE_VSI_TO_HW(vsi);
1117
1118 /* Can't find it, return an error */
1119 f = ice_find_vlan_filter(vsi, vlan);
1120 if (!f)
1121 return -EINVAL;
1122
1123 INIT_LIST_HEAD(&list_head);
1124
1125 v_list_itr = (struct ice_fltr_list_entry *)
1126 ice_malloc(hw, sizeof(*v_list_itr));
1127 if (!v_list_itr) {
1128 ret = -ENOMEM;
1129 goto DONE;
1130 }
1131
1132 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1133 v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1134 v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1135 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1136 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1137 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1138 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1139 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1140
1141 LIST_ADD(&v_list_itr->list_entry, &list_head);
1142
1143 /* remove the vlan filter */
1144 ret = ice_remove_vlan(hw, &list_head);
1145 if (ret != ICE_SUCCESS) {
1146 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1147 ret = -EINVAL;
1148 goto DONE;
1149 }
1150
1151 /* Remove the vlan id from vlan list */
1152 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1153 rte_free(f);
1154 vsi->vlan_num--;
1155
1156 ret = 0;
1157 DONE:
1158 rte_free(v_list_itr);
1159 return ret;
1160 }
1161
1162 static int
ice_remove_all_mac_vlan_filters(struct ice_vsi * vsi)1163 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1164 {
1165 struct ice_mac_filter *m_f;
1166 struct ice_vlan_filter *v_f;
1167 void *temp;
1168 int ret = 0;
1169
1170 if (!vsi || !vsi->mac_num)
1171 return -EINVAL;
1172
1173 RTE_TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1174 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1175 if (ret != ICE_SUCCESS) {
1176 ret = -EINVAL;
1177 goto DONE;
1178 }
1179 }
1180
1181 if (vsi->vlan_num == 0)
1182 return 0;
1183
1184 RTE_TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1185 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1186 if (ret != ICE_SUCCESS) {
1187 ret = -EINVAL;
1188 goto DONE;
1189 }
1190 }
1191
1192 DONE:
1193 return ret;
1194 }
1195
1196 /* Enable IRQ0 */
1197 static void
ice_pf_enable_irq0(struct ice_hw * hw)1198 ice_pf_enable_irq0(struct ice_hw *hw)
1199 {
1200 /* reset the registers */
1201 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1202 ICE_READ_REG(hw, PFINT_OICR);
1203
1204 #ifdef ICE_LSE_SPT
1205 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1206 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1207 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1208
1209 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1210 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1211 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1212 PFINT_OICR_CTL_ITR_INDX_M) |
1213 PFINT_OICR_CTL_CAUSE_ENA_M);
1214
1215 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1216 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1217 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1218 PFINT_FW_CTL_ITR_INDX_M) |
1219 PFINT_FW_CTL_CAUSE_ENA_M);
1220 #else
1221 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1222 #endif
1223
1224 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1225 GLINT_DYN_CTL_INTENA_M |
1226 GLINT_DYN_CTL_CLEARPBA_M |
1227 GLINT_DYN_CTL_ITR_INDX_M);
1228
1229 ice_flush(hw);
1230 }
1231
1232 /* Disable IRQ0 */
1233 static void
ice_pf_disable_irq0(struct ice_hw * hw)1234 ice_pf_disable_irq0(struct ice_hw *hw)
1235 {
1236 /* Disable all interrupt types */
1237 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1238 ice_flush(hw);
1239 }
1240
1241 #ifdef ICE_LSE_SPT
1242 static void
ice_handle_aq_msg(struct rte_eth_dev * dev)1243 ice_handle_aq_msg(struct rte_eth_dev *dev)
1244 {
1245 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 struct ice_ctl_q_info *cq = &hw->adminq;
1247 struct ice_rq_event_info event;
1248 uint16_t pending, opcode;
1249 int ret;
1250
1251 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1252 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1253 if (!event.msg_buf) {
1254 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1255 return;
1256 }
1257
1258 pending = 1;
1259 while (pending) {
1260 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1261
1262 if (ret != ICE_SUCCESS) {
1263 PMD_DRV_LOG(INFO,
1264 "Failed to read msg from AdminQ, "
1265 "adminq_err: %u",
1266 hw->adminq.sq_last_status);
1267 break;
1268 }
1269 opcode = rte_le_to_cpu_16(event.desc.opcode);
1270
1271 switch (opcode) {
1272 case ice_aqc_opc_get_link_status:
1273 ret = ice_link_update(dev, 0);
1274 if (!ret)
1275 rte_eth_dev_callback_process
1276 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1277 break;
1278 default:
1279 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1280 opcode);
1281 break;
1282 }
1283 }
1284 rte_free(event.msg_buf);
1285 }
1286 #endif
1287
1288 /**
1289 * Interrupt handler triggered by NIC for handling
1290 * specific interrupt.
1291 *
1292 * @param handle
1293 * Pointer to interrupt handle.
1294 * @param param
1295 * The address of parameter (struct rte_eth_dev *) registered before.
1296 *
1297 * @return
1298 * void
1299 */
1300 static void
ice_interrupt_handler(void * param)1301 ice_interrupt_handler(void *param)
1302 {
1303 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1304 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305 uint32_t oicr;
1306 uint32_t reg;
1307 uint8_t pf_num;
1308 uint8_t event;
1309 uint16_t queue;
1310 int ret;
1311 #ifdef ICE_LSE_SPT
1312 uint32_t int_fw_ctl;
1313 #endif
1314
1315 /* Disable interrupt */
1316 ice_pf_disable_irq0(hw);
1317
1318 /* read out interrupt causes */
1319 oicr = ICE_READ_REG(hw, PFINT_OICR);
1320 #ifdef ICE_LSE_SPT
1321 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1322 #endif
1323
1324 /* No interrupt event indicated */
1325 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1326 PMD_DRV_LOG(INFO, "No interrupt event");
1327 goto done;
1328 }
1329
1330 #ifdef ICE_LSE_SPT
1331 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1332 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1333 ice_handle_aq_msg(dev);
1334 }
1335 #else
1336 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1337 PMD_DRV_LOG(INFO, "OICR: link state change event");
1338 ret = ice_link_update(dev, 0);
1339 if (!ret)
1340 rte_eth_dev_callback_process
1341 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1342 }
1343 #endif
1344
1345 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1346 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1347 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1348 if (reg & GL_MDET_TX_PQM_VALID_M) {
1349 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1350 GL_MDET_TX_PQM_PF_NUM_S;
1351 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1352 GL_MDET_TX_PQM_MAL_TYPE_S;
1353 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1354 GL_MDET_TX_PQM_QNUM_S;
1355
1356 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1357 "%d by PQM on TX queue %d PF# %d",
1358 event, queue, pf_num);
1359 }
1360
1361 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1362 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1363 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1364 GL_MDET_TX_TCLAN_PF_NUM_S;
1365 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1366 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1367 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1368 GL_MDET_TX_TCLAN_QNUM_S;
1369
1370 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1371 "%d by TCLAN on TX queue %d PF# %d",
1372 event, queue, pf_num);
1373 }
1374 }
1375 done:
1376 /* Enable interrupt */
1377 ice_pf_enable_irq0(hw);
1378 rte_intr_ack(dev->intr_handle);
1379 }
1380
1381 static void
ice_init_proto_xtr(struct rte_eth_dev * dev)1382 ice_init_proto_xtr(struct rte_eth_dev *dev)
1383 {
1384 struct ice_adapter *ad =
1385 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1386 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1388 const struct proto_xtr_ol_flag *ol_flag;
1389 bool proto_xtr_enable = false;
1390 int offset;
1391 uint16_t i;
1392
1393 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1394 if (unlikely(pf->proto_xtr == NULL)) {
1395 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1396 return;
1397 }
1398
1399 for (i = 0; i < pf->lan_nb_qps; i++) {
1400 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1401 ad->devargs.proto_xtr[i] :
1402 ad->devargs.proto_xtr_dflt;
1403
1404 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1405 uint8_t type = pf->proto_xtr[i];
1406
1407 ice_proto_xtr_ol_flag_params[type].required = true;
1408 proto_xtr_enable = true;
1409 }
1410 }
1411
1412 if (likely(!proto_xtr_enable))
1413 return;
1414
1415 ice_check_proto_xtr_support(hw);
1416
1417 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1418 if (unlikely(offset == -1)) {
1419 PMD_DRV_LOG(ERR,
1420 "Protocol extraction metadata is disabled in mbuf with error %d",
1421 -rte_errno);
1422 return;
1423 }
1424
1425 PMD_DRV_LOG(DEBUG,
1426 "Protocol extraction metadata offset in mbuf is : %d",
1427 offset);
1428 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1429
1430 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1431 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1432
1433 if (!ol_flag->required)
1434 continue;
1435
1436 if (!ice_proto_xtr_hw_support[i]) {
1437 PMD_DRV_LOG(ERR,
1438 "Protocol extraction type %u is not supported in hardware",
1439 i);
1440 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1441 break;
1442 }
1443
1444 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1445 if (unlikely(offset == -1)) {
1446 PMD_DRV_LOG(ERR,
1447 "Protocol extraction offload '%s' failed to register with error %d",
1448 ol_flag->param.name, -rte_errno);
1449
1450 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1451 break;
1452 }
1453
1454 PMD_DRV_LOG(DEBUG,
1455 "Protocol extraction offload '%s' offset in mbuf is : %d",
1456 ol_flag->param.name, offset);
1457 *ol_flag->ol_flag = 1ULL << offset;
1458 }
1459 }
1460
1461 /* Initialize SW parameters of PF */
1462 static int
ice_pf_sw_init(struct rte_eth_dev * dev)1463 ice_pf_sw_init(struct rte_eth_dev *dev)
1464 {
1465 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1466 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1467
1468 pf->lan_nb_qp_max =
1469 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1470 hw->func_caps.common_cap.num_rxq);
1471
1472 pf->lan_nb_qps = pf->lan_nb_qp_max;
1473
1474 ice_init_proto_xtr(dev);
1475
1476 if (hw->func_caps.fd_fltr_guar > 0 ||
1477 hw->func_caps.fd_fltr_best_effort > 0) {
1478 pf->flags |= ICE_FLAG_FDIR;
1479 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1480 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1481 } else {
1482 pf->fdir_nb_qps = 0;
1483 }
1484 pf->fdir_qp_offset = 0;
1485
1486 return 0;
1487 }
1488
1489 struct ice_vsi *
ice_setup_vsi(struct ice_pf * pf,enum ice_vsi_type type)1490 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1491 {
1492 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1493 struct ice_vsi *vsi = NULL;
1494 struct ice_vsi_ctx vsi_ctx;
1495 int ret;
1496 struct rte_ether_addr broadcast = {
1497 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1498 struct rte_ether_addr mac_addr;
1499 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1500 uint8_t tc_bitmap = 0x1;
1501 uint16_t cfg;
1502
1503 /* hw->num_lports = 1 in NIC mode */
1504 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1505 if (!vsi)
1506 return NULL;
1507
1508 vsi->idx = pf->next_vsi_idx;
1509 pf->next_vsi_idx++;
1510 vsi->type = type;
1511 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1512 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1513 vsi->vlan_anti_spoof_on = 0;
1514 vsi->vlan_filter_on = 1;
1515 TAILQ_INIT(&vsi->mac_list);
1516 TAILQ_INIT(&vsi->vlan_list);
1517
1518 /* Be sync with RTE_ETH_RSS_RETA_SIZE_x maximum value definition */
1519 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1520 RTE_ETH_RSS_RETA_SIZE_512 ? RTE_ETH_RSS_RETA_SIZE_512 :
1521 hw->func_caps.common_cap.rss_table_size;
1522 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1523
1524 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1525 switch (type) {
1526 case ICE_VSI_PF:
1527 vsi->nb_qps = pf->lan_nb_qps;
1528 vsi->base_queue = 1;
1529 ice_vsi_config_default_rss(&vsi_ctx.info);
1530 vsi_ctx.alloc_from_pool = true;
1531 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1532 /* switch_id is queried by get_switch_config aq, which is done
1533 * by ice_init_hw
1534 */
1535 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1536 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1537 /* Allow all untagged or tagged packets */
1538 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1539 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1540 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1541 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1542 if (ice_is_dvm_ena(hw)) {
1543 vsi_ctx.info.outer_vlan_flags =
1544 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1545 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1546 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1547 vsi_ctx.info.outer_vlan_flags |=
1548 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1549 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1550 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1551 }
1552
1553 /* FDIR */
1554 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1555 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1556 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1557 cfg = ICE_AQ_VSI_FD_ENABLE;
1558 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1559 vsi_ctx.info.max_fd_fltr_dedicated =
1560 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1561 vsi_ctx.info.max_fd_fltr_shared =
1562 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1563
1564 /* Enable VLAN/UP trip */
1565 ret = ice_vsi_config_tc_queue_mapping(vsi,
1566 &vsi_ctx.info,
1567 ICE_DEFAULT_TCMAP);
1568 if (ret) {
1569 PMD_INIT_LOG(ERR,
1570 "tc queue mapping with vsi failed, "
1571 "err = %d",
1572 ret);
1573 goto fail_mem;
1574 }
1575
1576 break;
1577 case ICE_VSI_CTRL:
1578 vsi->nb_qps = pf->fdir_nb_qps;
1579 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1580 vsi_ctx.alloc_from_pool = true;
1581 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1582
1583 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1584 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1585 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1586 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1587 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1588 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1589 ret = ice_vsi_config_tc_queue_mapping(vsi,
1590 &vsi_ctx.info,
1591 ICE_DEFAULT_TCMAP);
1592 if (ret) {
1593 PMD_INIT_LOG(ERR,
1594 "tc queue mapping with vsi failed, "
1595 "err = %d",
1596 ret);
1597 goto fail_mem;
1598 }
1599 break;
1600 default:
1601 /* for other types of VSI */
1602 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1603 goto fail_mem;
1604 }
1605
1606 /* VF has MSIX interrupt in VF range, don't allocate here */
1607 if (type == ICE_VSI_PF) {
1608 ret = ice_res_pool_alloc(&pf->msix_pool,
1609 RTE_MIN(vsi->nb_qps,
1610 RTE_MAX_RXTX_INTR_VEC_ID));
1611 if (ret < 0) {
1612 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1613 vsi->vsi_id, ret);
1614 }
1615 vsi->msix_intr = ret;
1616 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1617 } else if (type == ICE_VSI_CTRL) {
1618 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1619 if (ret < 0) {
1620 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1621 vsi->vsi_id, ret);
1622 }
1623 vsi->msix_intr = ret;
1624 vsi->nb_msix = 1;
1625 } else {
1626 vsi->msix_intr = 0;
1627 vsi->nb_msix = 0;
1628 }
1629 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1630 if (ret != ICE_SUCCESS) {
1631 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1632 goto fail_mem;
1633 }
1634 /* store vsi information is SW structure */
1635 vsi->vsi_id = vsi_ctx.vsi_num;
1636 vsi->info = vsi_ctx.info;
1637 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1638 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1639
1640 if (type == ICE_VSI_PF) {
1641 /* MAC configuration */
1642 rte_ether_addr_copy((struct rte_ether_addr *)
1643 hw->port_info->mac.perm_addr,
1644 &pf->dev_addr);
1645
1646 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1647 ret = ice_add_mac_filter(vsi, &mac_addr);
1648 if (ret != ICE_SUCCESS)
1649 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1650
1651 rte_ether_addr_copy(&broadcast, &mac_addr);
1652 ret = ice_add_mac_filter(vsi, &mac_addr);
1653 if (ret != ICE_SUCCESS)
1654 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1655 }
1656
1657 /* At the beginning, only TC0. */
1658 /* What we need here is the maximum number of the TX queues.
1659 * Currently vsi->nb_qps means it.
1660 * Correct it if any change.
1661 */
1662 max_txqs[0] = vsi->nb_qps;
1663 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1664 tc_bitmap, max_txqs);
1665 if (ret != ICE_SUCCESS)
1666 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1667
1668 return vsi;
1669 fail_mem:
1670 rte_free(vsi);
1671 pf->next_vsi_idx--;
1672 return NULL;
1673 }
1674
1675 static int
ice_send_driver_ver(struct ice_hw * hw)1676 ice_send_driver_ver(struct ice_hw *hw)
1677 {
1678 struct ice_driver_ver dv;
1679
1680 /* we don't have driver version use 0 for dummy */
1681 dv.major_ver = 0;
1682 dv.minor_ver = 0;
1683 dv.build_ver = 0;
1684 dv.subbuild_ver = 0;
1685 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1686
1687 return ice_aq_send_driver_ver(hw, &dv, NULL);
1688 }
1689
1690 static int
ice_pf_setup(struct ice_pf * pf)1691 ice_pf_setup(struct ice_pf *pf)
1692 {
1693 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1694 struct ice_vsi *vsi;
1695 uint16_t unused;
1696
1697 /* Clear all stats counters */
1698 pf->offset_loaded = false;
1699 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1700 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1701 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1702 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1703
1704 /* force guaranteed filter pool for PF */
1705 ice_alloc_fd_guar_item(hw, &unused,
1706 hw->func_caps.fd_fltr_guar);
1707 /* force shared filter pool for PF */
1708 ice_alloc_fd_shrd_item(hw, &unused,
1709 hw->func_caps.fd_fltr_best_effort);
1710
1711 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1712 if (!vsi) {
1713 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1714 return -EINVAL;
1715 }
1716
1717 pf->main_vsi = vsi;
1718
1719 return 0;
1720 }
1721
1722 static enum ice_pkg_type
ice_load_pkg_type(struct ice_hw * hw)1723 ice_load_pkg_type(struct ice_hw *hw)
1724 {
1725 enum ice_pkg_type package_type;
1726
1727 /* store the activated package type (OS default or Comms) */
1728 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1729 ICE_PKG_NAME_SIZE))
1730 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1731 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1732 ICE_PKG_NAME_SIZE))
1733 package_type = ICE_PKG_TYPE_COMMS;
1734 else
1735 package_type = ICE_PKG_TYPE_UNKNOWN;
1736
1737 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1738 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1739 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1740 hw->active_pkg_name,
1741 ice_is_dvm_ena(hw) ? "double" : "single");
1742
1743 return package_type;
1744 }
1745
ice_load_pkg(struct ice_adapter * adapter,bool use_dsn,uint64_t dsn)1746 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1747 {
1748 struct ice_hw *hw = &adapter->hw;
1749 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1750 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1751 void *buf;
1752 size_t bufsz;
1753 int err;
1754
1755 if (!use_dsn)
1756 goto no_dsn;
1757
1758 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1759 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1760 "ice-%016" PRIx64 ".pkg", dsn);
1761 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1762 ICE_MAX_PKG_FILENAME_SIZE);
1763 strcat(pkg_file, opt_ddp_filename);
1764 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1765 goto load_fw;
1766
1767 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1768 ICE_MAX_PKG_FILENAME_SIZE);
1769 strcat(pkg_file, opt_ddp_filename);
1770 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1771 goto load_fw;
1772
1773 no_dsn:
1774 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1775 if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1776 goto load_fw;
1777
1778 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1779 if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1780 PMD_INIT_LOG(ERR, "failed to search file path\n");
1781 return -1;
1782 }
1783
1784 load_fw:
1785 PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1786
1787 err = ice_copy_and_init_pkg(hw, buf, bufsz);
1788 if (err) {
1789 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1790 goto out;
1791 }
1792
1793 /* store the loaded pkg type info */
1794 adapter->active_pkg_type = ice_load_pkg_type(hw);
1795
1796 out:
1797 free(buf);
1798 return err;
1799 }
1800
1801 static void
ice_base_queue_get(struct ice_pf * pf)1802 ice_base_queue_get(struct ice_pf *pf)
1803 {
1804 uint32_t reg;
1805 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1806
1807 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1808 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1809 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1810 } else {
1811 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1812 " index");
1813 }
1814 }
1815
1816 static int
parse_bool(const char * key,const char * value,void * args)1817 parse_bool(const char *key, const char *value, void *args)
1818 {
1819 int *i = (int *)args;
1820 char *end;
1821 int num;
1822
1823 num = strtoul(value, &end, 10);
1824
1825 if (num != 0 && num != 1) {
1826 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1827 "value must be 0 or 1",
1828 value, key);
1829 return -1;
1830 }
1831
1832 *i = num;
1833 return 0;
1834 }
1835
1836 static int
parse_u64(const char * key,const char * value,void * args)1837 parse_u64(const char *key, const char *value, void *args)
1838 {
1839 u64 *num = (u64 *)args;
1840 u64 tmp;
1841
1842 errno = 0;
1843 tmp = strtoull(value, NULL, 16);
1844 if (errno) {
1845 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1846 key, value);
1847 return -1;
1848 }
1849
1850 *num = tmp;
1851
1852 return 0;
1853 }
1854
1855 static int
lookup_pps_type(const char * pps_name)1856 lookup_pps_type(const char *pps_name)
1857 {
1858 static struct {
1859 const char *name;
1860 enum pps_type type;
1861 } pps_type_map[] = {
1862 { "pin", PPS_PIN },
1863 };
1864
1865 uint32_t i;
1866
1867 for (i = 0; i < RTE_DIM(pps_type_map); i++) {
1868 if (strcmp(pps_name, pps_type_map[i].name) == 0)
1869 return pps_type_map[i].type;
1870 }
1871
1872 return -1;
1873 }
1874
1875 static int
parse_pin_set(const char * input,int pps_type,struct ice_devargs * devargs)1876 parse_pin_set(const char *input, int pps_type, struct ice_devargs *devargs)
1877 {
1878 const char *str = input;
1879 char *end = NULL;
1880 uint32_t idx;
1881
1882 while (isblank(*str))
1883 str++;
1884
1885 if (!isdigit(*str))
1886 return -1;
1887
1888 if (pps_type == PPS_PIN) {
1889 idx = strtoul(str, &end, 10);
1890 if (end == NULL || idx >= ICE_MAX_PIN_NUM)
1891 return -1;
1892 while (isblank(*end))
1893 end++;
1894 if (*end != ']')
1895 return -1;
1896
1897 devargs->pin_idx = idx;
1898 devargs->pps_out_ena = 1;
1899
1900 return 0;
1901 }
1902
1903 return -1;
1904 }
1905
1906 static int
parse_pps_out_parameter(const char * pins,struct ice_devargs * devargs)1907 parse_pps_out_parameter(const char *pins, struct ice_devargs *devargs)
1908 {
1909 const char *pin_start;
1910 uint32_t idx;
1911 int pps_type;
1912 char pps_name[32];
1913
1914 while (isblank(*pins))
1915 pins++;
1916
1917 pins++;
1918 while (isblank(*pins))
1919 pins++;
1920 if (*pins == '\0')
1921 return -1;
1922
1923 for (idx = 0; ; idx++) {
1924 if (isblank(pins[idx]) ||
1925 pins[idx] == ':' ||
1926 pins[idx] == '\0')
1927 break;
1928
1929 pps_name[idx] = pins[idx];
1930 }
1931 pps_name[idx] = '\0';
1932 pps_type = lookup_pps_type(pps_name);
1933 if (pps_type < 0)
1934 return -1;
1935
1936 pins += idx;
1937
1938 pins += strcspn(pins, ":");
1939 if (*pins++ != ':')
1940 return -1;
1941 while (isblank(*pins))
1942 pins++;
1943
1944 pin_start = pins;
1945
1946 while (isblank(*pins))
1947 pins++;
1948
1949 if (parse_pin_set(pin_start, pps_type, devargs) < 0)
1950 return -1;
1951
1952 return 0;
1953 }
1954
1955 static int
handle_pps_out_arg(__rte_unused const char * key,const char * value,void * extra_args)1956 handle_pps_out_arg(__rte_unused const char *key, const char *value,
1957 void *extra_args)
1958 {
1959 struct ice_devargs *devargs = extra_args;
1960
1961 if (value == NULL || extra_args == NULL)
1962 return -EINVAL;
1963
1964 if (parse_pps_out_parameter(value, devargs) < 0) {
1965 PMD_DRV_LOG(ERR,
1966 "The GPIO pin parameter is wrong : '%s'",
1967 value);
1968 return -1;
1969 }
1970
1971 return 0;
1972 }
1973
ice_parse_devargs(struct rte_eth_dev * dev)1974 static int ice_parse_devargs(struct rte_eth_dev *dev)
1975 {
1976 struct ice_adapter *ad =
1977 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1978 struct rte_devargs *devargs = dev->device->devargs;
1979 struct rte_kvargs *kvlist;
1980 int ret;
1981
1982 if (devargs == NULL)
1983 return 0;
1984
1985 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1986 if (kvlist == NULL) {
1987 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1988 return -EINVAL;
1989 }
1990
1991 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1992 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1993 sizeof(ad->devargs.proto_xtr));
1994
1995 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1996 &handle_proto_xtr_arg, &ad->devargs);
1997 if (ret)
1998 goto bail;
1999
2000 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
2001 &parse_bool, &ad->devargs.safe_mode_support);
2002 if (ret)
2003 goto bail;
2004
2005 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
2006 &parse_bool, &ad->devargs.pipe_mode_support);
2007 if (ret)
2008 goto bail;
2009
2010 ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
2011 &parse_u64, &ad->hw.debug_mask);
2012 if (ret)
2013 goto bail;
2014
2015 ret = rte_kvargs_process(kvlist, ICE_ONE_PPS_OUT_ARG,
2016 &handle_pps_out_arg, &ad->devargs);
2017 if (ret)
2018 goto bail;
2019
2020 ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG,
2021 &parse_bool, &ad->devargs.rx_low_latency);
2022
2023 bail:
2024 rte_kvargs_free(kvlist);
2025 return ret;
2026 }
2027
2028 /* Forward LLDP packets to default VSI by set switch rules */
2029 static int
ice_vsi_config_sw_lldp(struct ice_vsi * vsi,bool on)2030 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2031 {
2032 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2033 struct ice_fltr_list_entry *s_list_itr = NULL;
2034 struct LIST_HEAD_TYPE list_head;
2035 int ret = 0;
2036
2037 INIT_LIST_HEAD(&list_head);
2038
2039 s_list_itr = (struct ice_fltr_list_entry *)
2040 ice_malloc(hw, sizeof(*s_list_itr));
2041 if (!s_list_itr)
2042 return -ENOMEM;
2043 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2044 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2045 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2046 RTE_ETHER_TYPE_LLDP;
2047 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2048 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2049 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2050 LIST_ADD(&s_list_itr->list_entry, &list_head);
2051 if (on)
2052 ret = ice_add_eth_mac(hw, &list_head);
2053 else
2054 ret = ice_remove_eth_mac(hw, &list_head);
2055
2056 rte_free(s_list_itr);
2057 return ret;
2058 }
2059
2060 static enum ice_status
ice_get_hw_res(struct ice_hw * hw,uint16_t res_type,uint16_t num,uint16_t desc_id,uint16_t * prof_buf,uint16_t * num_prof)2061 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2062 uint16_t num, uint16_t desc_id,
2063 uint16_t *prof_buf, uint16_t *num_prof)
2064 {
2065 struct ice_aqc_res_elem *resp_buf;
2066 int ret;
2067 uint16_t buf_len;
2068 bool res_shared = 1;
2069 struct ice_aq_desc aq_desc;
2070 struct ice_sq_cd *cd = NULL;
2071 struct ice_aqc_get_allocd_res_desc *cmd =
2072 &aq_desc.params.get_res_desc;
2073
2074 buf_len = sizeof(*resp_buf) * num;
2075 resp_buf = ice_malloc(hw, buf_len);
2076 if (!resp_buf)
2077 return -ENOMEM;
2078
2079 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2080 ice_aqc_opc_get_allocd_res_desc);
2081
2082 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2083 ICE_AQC_RES_TYPE_M) | (res_shared ?
2084 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2085 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2086
2087 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2088 if (!ret)
2089 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2090 else
2091 goto exit;
2092
2093 ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
2094 (*num_prof), ICE_NONDMA_TO_NONDMA);
2095
2096 exit:
2097 rte_free(resp_buf);
2098 return ret;
2099 }
2100 static int
ice_cleanup_resource(struct ice_hw * hw,uint16_t res_type)2101 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2102 {
2103 int ret;
2104 uint16_t prof_id;
2105 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2106 uint16_t first_desc = 1;
2107 uint16_t num_prof = 0;
2108
2109 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2110 first_desc, prof_buf, &num_prof);
2111 if (ret) {
2112 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2113 return ret;
2114 }
2115
2116 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2117 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2118 if (ret) {
2119 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2120 return ret;
2121 }
2122 }
2123 return 0;
2124 }
2125
2126 static int
ice_reset_fxp_resource(struct ice_hw * hw)2127 ice_reset_fxp_resource(struct ice_hw *hw)
2128 {
2129 int ret;
2130
2131 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2132 if (ret) {
2133 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2134 return ret;
2135 }
2136
2137 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2138 if (ret) {
2139 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2140 return ret;
2141 }
2142
2143 return 0;
2144 }
2145
2146 static void
ice_rss_ctx_init(struct ice_pf * pf)2147 ice_rss_ctx_init(struct ice_pf *pf)
2148 {
2149 memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
2150 }
2151
2152 static uint64_t
ice_get_supported_rxdid(struct ice_hw * hw)2153 ice_get_supported_rxdid(struct ice_hw *hw)
2154 {
2155 uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
2156 uint32_t regval;
2157 int i;
2158
2159 supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
2160
2161 for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
2162 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2163 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2164 & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2165 supported_rxdid |= BIT(i);
2166 }
2167 return supported_rxdid;
2168 }
2169
2170 static int
ice_dev_init(struct rte_eth_dev * dev)2171 ice_dev_init(struct rte_eth_dev *dev)
2172 {
2173 struct rte_pci_device *pci_dev;
2174 struct rte_intr_handle *intr_handle;
2175 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2177 struct ice_adapter *ad =
2178 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2179 struct ice_vsi *vsi;
2180 int ret;
2181 #ifndef RTE_EXEC_ENV_WINDOWS
2182 off_t pos;
2183 uint32_t dsn_low, dsn_high;
2184 uint64_t dsn;
2185 bool use_dsn;
2186 #endif
2187
2188 dev->dev_ops = &ice_eth_dev_ops;
2189 dev->rx_queue_count = ice_rx_queue_count;
2190 dev->rx_descriptor_status = ice_rx_descriptor_status;
2191 dev->tx_descriptor_status = ice_tx_descriptor_status;
2192 dev->rx_pkt_burst = ice_recv_pkts;
2193 dev->tx_pkt_burst = ice_xmit_pkts;
2194 dev->tx_pkt_prepare = ice_prep_pkts;
2195
2196 /* for secondary processes, we don't initialise any further as primary
2197 * has already done this work.
2198 */
2199 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2200 ice_set_rx_function(dev);
2201 ice_set_tx_function(dev);
2202 return 0;
2203 }
2204
2205 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2206
2207 ice_set_default_ptype_table(dev);
2208 pci_dev = RTE_DEV_TO_PCI(dev->device);
2209 intr_handle = pci_dev->intr_handle;
2210
2211 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2212 pf->dev_data = dev->data;
2213 hw->back = pf->adapter;
2214 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2215 hw->vendor_id = pci_dev->id.vendor_id;
2216 hw->device_id = pci_dev->id.device_id;
2217 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2218 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2219 hw->bus.device = pci_dev->addr.devid;
2220 hw->bus.func = pci_dev->addr.function;
2221
2222 ret = ice_parse_devargs(dev);
2223 if (ret) {
2224 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2225 return -EINVAL;
2226 }
2227
2228 ice_init_controlq_parameter(hw);
2229
2230 ret = ice_init_hw(hw);
2231 if (ret) {
2232 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2233 return -EINVAL;
2234 }
2235
2236 #ifndef RTE_EXEC_ENV_WINDOWS
2237 use_dsn = false;
2238 dsn = 0;
2239 pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2240 if (pos) {
2241 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2242 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2243 PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2244 } else {
2245 use_dsn = true;
2246 dsn = (uint64_t)dsn_high << 32 | dsn_low;
2247 }
2248 } else {
2249 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2250 }
2251
2252 ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2253 if (ret == 0) {
2254 ret = ice_init_hw_tbls(hw);
2255 if (ret) {
2256 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2257 rte_free(hw->pkg_copy);
2258 }
2259 }
2260
2261 if (ret) {
2262 if (ad->devargs.safe_mode_support == 0) {
2263 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2264 "Use safe-mode-support=1 to enter Safe Mode");
2265 goto err_init_fw;
2266 }
2267
2268 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2269 "Entering Safe Mode");
2270 ad->is_safe_mode = 1;
2271 }
2272 #endif
2273
2274 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2275 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2276 hw->api_maj_ver, hw->api_min_ver);
2277
2278 ice_pf_sw_init(dev);
2279 ret = ice_init_mac_address(dev);
2280 if (ret) {
2281 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2282 goto err_init_mac;
2283 }
2284
2285 ret = ice_res_pool_init(&pf->msix_pool, 1,
2286 hw->func_caps.common_cap.num_msix_vectors - 1);
2287 if (ret) {
2288 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2289 goto err_msix_pool_init;
2290 }
2291
2292 ret = ice_pf_setup(pf);
2293 if (ret) {
2294 PMD_INIT_LOG(ERR, "Failed to setup PF");
2295 goto err_pf_setup;
2296 }
2297
2298 ret = ice_send_driver_ver(hw);
2299 if (ret) {
2300 PMD_INIT_LOG(ERR, "Failed to send driver version");
2301 goto err_pf_setup;
2302 }
2303
2304 vsi = pf->main_vsi;
2305
2306 ret = ice_aq_stop_lldp(hw, true, false, NULL);
2307 if (ret != ICE_SUCCESS)
2308 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2309 ret = ice_init_dcb(hw, true);
2310 if (ret != ICE_SUCCESS)
2311 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2312 /* Forward LLDP packets to default VSI */
2313 ret = ice_vsi_config_sw_lldp(vsi, true);
2314 if (ret != ICE_SUCCESS)
2315 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2316 /* register callback func to eal lib */
2317 rte_intr_callback_register(intr_handle,
2318 ice_interrupt_handler, dev);
2319
2320 ice_pf_enable_irq0(hw);
2321
2322 /* enable uio intr after callback register */
2323 rte_intr_enable(intr_handle);
2324
2325 /* get base queue pairs index in the device */
2326 ice_base_queue_get(pf);
2327
2328 /* Initialize RSS context for gtpu_eh */
2329 ice_rss_ctx_init(pf);
2330
2331 if (!ad->is_safe_mode) {
2332 ret = ice_flow_init(ad);
2333 if (ret) {
2334 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2335 goto err_flow_init;
2336 }
2337 }
2338
2339 ret = ice_reset_fxp_resource(hw);
2340 if (ret) {
2341 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2342 goto err_flow_init;
2343 }
2344
2345 pf->supported_rxdid = ice_get_supported_rxdid(hw);
2346
2347 return 0;
2348
2349 err_flow_init:
2350 ice_flow_uninit(ad);
2351 rte_intr_disable(intr_handle);
2352 ice_pf_disable_irq0(hw);
2353 rte_intr_callback_unregister(intr_handle,
2354 ice_interrupt_handler, dev);
2355 err_pf_setup:
2356 ice_res_pool_destroy(&pf->msix_pool);
2357 err_msix_pool_init:
2358 rte_free(dev->data->mac_addrs);
2359 dev->data->mac_addrs = NULL;
2360 err_init_mac:
2361 rte_free(pf->proto_xtr);
2362 #ifndef RTE_EXEC_ENV_WINDOWS
2363 err_init_fw:
2364 #endif
2365 ice_deinit_hw(hw);
2366
2367 return ret;
2368 }
2369
2370 int
ice_release_vsi(struct ice_vsi * vsi)2371 ice_release_vsi(struct ice_vsi *vsi)
2372 {
2373 struct ice_hw *hw;
2374 struct ice_vsi_ctx vsi_ctx;
2375 enum ice_status ret;
2376 int error = 0;
2377
2378 if (!vsi)
2379 return error;
2380
2381 hw = ICE_VSI_TO_HW(vsi);
2382
2383 ice_remove_all_mac_vlan_filters(vsi);
2384
2385 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2386
2387 vsi_ctx.vsi_num = vsi->vsi_id;
2388 vsi_ctx.info = vsi->info;
2389 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2390 if (ret != ICE_SUCCESS) {
2391 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2392 error = -1;
2393 }
2394
2395 rte_free(vsi->rss_lut);
2396 rte_free(vsi->rss_key);
2397 rte_free(vsi);
2398 return error;
2399 }
2400
2401 void
ice_vsi_disable_queues_intr(struct ice_vsi * vsi)2402 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2403 {
2404 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2405 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2406 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2407 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2408 uint16_t msix_intr, i;
2409
2410 /* disable interrupt and also clear all the exist config */
2411 for (i = 0; i < vsi->nb_qps; i++) {
2412 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2413 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2414 rte_wmb();
2415 }
2416
2417 if (rte_intr_allow_others(intr_handle))
2418 /* vfio-pci */
2419 for (i = 0; i < vsi->nb_msix; i++) {
2420 msix_intr = vsi->msix_intr + i;
2421 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2422 GLINT_DYN_CTL_WB_ON_ITR_M);
2423 }
2424 else
2425 /* igb_uio */
2426 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2427 }
2428
2429 static int
ice_dev_stop(struct rte_eth_dev * dev)2430 ice_dev_stop(struct rte_eth_dev *dev)
2431 {
2432 struct rte_eth_dev_data *data = dev->data;
2433 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2434 struct ice_vsi *main_vsi = pf->main_vsi;
2435 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2436 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2437 uint16_t i;
2438
2439 /* avoid stopping again */
2440 if (pf->adapter_stopped)
2441 return 0;
2442
2443 /* stop and clear all Rx queues */
2444 for (i = 0; i < data->nb_rx_queues; i++)
2445 ice_rx_queue_stop(dev, i);
2446
2447 /* stop and clear all Tx queues */
2448 for (i = 0; i < data->nb_tx_queues; i++)
2449 ice_tx_queue_stop(dev, i);
2450
2451 /* disable all queue interrupts */
2452 ice_vsi_disable_queues_intr(main_vsi);
2453
2454 if (pf->init_link_up)
2455 ice_dev_set_link_up(dev);
2456 else
2457 ice_dev_set_link_down(dev);
2458
2459 /* Clean datapath event and queue/vec mapping */
2460 rte_intr_efd_disable(intr_handle);
2461 rte_intr_vec_list_free(intr_handle);
2462
2463 pf->adapter_stopped = true;
2464 dev->data->dev_started = 0;
2465
2466 return 0;
2467 }
2468
2469 static int
ice_dev_close(struct rte_eth_dev * dev)2470 ice_dev_close(struct rte_eth_dev *dev)
2471 {
2472 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2473 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2475 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2476 struct ice_adapter *ad =
2477 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2478 int ret;
2479 uint32_t val;
2480 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
2481 uint32_t pin_idx = ad->devargs.pin_idx;
2482
2483 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2484 return 0;
2485
2486 /* Since stop will make link down, then the link event will be
2487 * triggered, disable the irq firstly to avoid the port_infoe etc
2488 * resources deallocation causing the interrupt service thread
2489 * crash.
2490 */
2491 ice_pf_disable_irq0(hw);
2492
2493 ret = ice_dev_stop(dev);
2494
2495 if (!ad->is_safe_mode)
2496 ice_flow_uninit(ad);
2497
2498 /* release all queue resource */
2499 ice_free_queues(dev);
2500
2501 ice_res_pool_destroy(&pf->msix_pool);
2502 ice_release_vsi(pf->main_vsi);
2503 ice_sched_cleanup_all(hw);
2504 ice_free_hw_tbls(hw);
2505 rte_free(hw->port_info);
2506 hw->port_info = NULL;
2507 ice_shutdown_all_ctrlq(hw);
2508 rte_free(pf->proto_xtr);
2509 pf->proto_xtr = NULL;
2510
2511 if (ad->devargs.pps_out_ena) {
2512 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(pin_idx, timer), 0);
2513 ICE_WRITE_REG(hw, GLTSYN_CLKO(pin_idx, timer), 0);
2514 ICE_WRITE_REG(hw, GLTSYN_TGT_L(pin_idx, timer), 0);
2515 ICE_WRITE_REG(hw, GLTSYN_TGT_H(pin_idx, timer), 0);
2516
2517 val = GLGEN_GPIO_CTL_PIN_DIR_M;
2518 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(pin_idx), val);
2519 }
2520
2521 /* disable uio intr before callback unregister */
2522 rte_intr_disable(intr_handle);
2523
2524 /* unregister callback func from eal lib */
2525 rte_intr_callback_unregister(intr_handle,
2526 ice_interrupt_handler, dev);
2527
2528 return ret;
2529 }
2530
2531 static int
ice_dev_uninit(struct rte_eth_dev * dev)2532 ice_dev_uninit(struct rte_eth_dev *dev)
2533 {
2534 ice_dev_close(dev);
2535
2536 return 0;
2537 }
2538
2539 static bool
is_hash_cfg_valid(struct ice_rss_hash_cfg * cfg)2540 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2541 {
2542 return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2543 }
2544
2545 static void
hash_cfg_reset(struct ice_rss_hash_cfg * cfg)2546 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2547 {
2548 cfg->hash_flds = 0;
2549 cfg->addl_hdrs = 0;
2550 cfg->symm = 0;
2551 cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2552 }
2553
2554 static int
ice_hash_moveout(struct ice_pf * pf,struct ice_rss_hash_cfg * cfg)2555 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2556 {
2557 enum ice_status status = ICE_SUCCESS;
2558 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2559 struct ice_vsi *vsi = pf->main_vsi;
2560
2561 if (!is_hash_cfg_valid(cfg))
2562 return -ENOENT;
2563
2564 status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2565 if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2566 PMD_DRV_LOG(ERR,
2567 "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2568 vsi->idx, status);
2569 return -EBUSY;
2570 }
2571
2572 return 0;
2573 }
2574
2575 static int
ice_hash_moveback(struct ice_pf * pf,struct ice_rss_hash_cfg * cfg)2576 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2577 {
2578 enum ice_status status = ICE_SUCCESS;
2579 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2580 struct ice_vsi *vsi = pf->main_vsi;
2581
2582 if (!is_hash_cfg_valid(cfg))
2583 return -ENOENT;
2584
2585 status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2586 if (status) {
2587 PMD_DRV_LOG(ERR,
2588 "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2589 vsi->idx, status);
2590 return -EBUSY;
2591 }
2592
2593 return 0;
2594 }
2595
2596 static int
ice_hash_remove(struct ice_pf * pf,struct ice_rss_hash_cfg * cfg)2597 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2598 {
2599 int ret;
2600
2601 ret = ice_hash_moveout(pf, cfg);
2602 if (ret && (ret != -ENOENT))
2603 return ret;
2604
2605 hash_cfg_reset(cfg);
2606
2607 return 0;
2608 }
2609
2610 static int
ice_add_rss_cfg_pre_gtpu(struct ice_pf * pf,struct ice_hash_gtpu_ctx * ctx,u8 ctx_idx)2611 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2612 u8 ctx_idx)
2613 {
2614 int ret;
2615
2616 switch (ctx_idx) {
2617 case ICE_HASH_GTPU_CTX_EH_IP:
2618 ret = ice_hash_remove(pf,
2619 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2620 if (ret && (ret != -ENOENT))
2621 return ret;
2622
2623 ret = ice_hash_remove(pf,
2624 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2625 if (ret && (ret != -ENOENT))
2626 return ret;
2627
2628 ret = ice_hash_remove(pf,
2629 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2630 if (ret && (ret != -ENOENT))
2631 return ret;
2632
2633 ret = ice_hash_remove(pf,
2634 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2635 if (ret && (ret != -ENOENT))
2636 return ret;
2637
2638 ret = ice_hash_remove(pf,
2639 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2640 if (ret && (ret != -ENOENT))
2641 return ret;
2642
2643 ret = ice_hash_remove(pf,
2644 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2645 if (ret && (ret != -ENOENT))
2646 return ret;
2647
2648 ret = ice_hash_remove(pf,
2649 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2650 if (ret && (ret != -ENOENT))
2651 return ret;
2652
2653 ret = ice_hash_remove(pf,
2654 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2655 if (ret && (ret != -ENOENT))
2656 return ret;
2657
2658 break;
2659 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2660 ret = ice_hash_remove(pf,
2661 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2662 if (ret && (ret != -ENOENT))
2663 return ret;
2664
2665 ret = ice_hash_remove(pf,
2666 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2667 if (ret && (ret != -ENOENT))
2668 return ret;
2669
2670 ret = ice_hash_moveout(pf,
2671 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2672 if (ret && (ret != -ENOENT))
2673 return ret;
2674
2675 ret = ice_hash_moveout(pf,
2676 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2677 if (ret && (ret != -ENOENT))
2678 return ret;
2679
2680 ret = ice_hash_moveout(pf,
2681 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2682 if (ret && (ret != -ENOENT))
2683 return ret;
2684
2685 ret = ice_hash_moveout(pf,
2686 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2687 if (ret && (ret != -ENOENT))
2688 return ret;
2689
2690 break;
2691 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2692 ret = ice_hash_remove(pf,
2693 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2694 if (ret && (ret != -ENOENT))
2695 return ret;
2696
2697 ret = ice_hash_remove(pf,
2698 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2699 if (ret && (ret != -ENOENT))
2700 return ret;
2701
2702 ret = ice_hash_moveout(pf,
2703 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2704 if (ret && (ret != -ENOENT))
2705 return ret;
2706
2707 ret = ice_hash_moveout(pf,
2708 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2709 if (ret && (ret != -ENOENT))
2710 return ret;
2711
2712 ret = ice_hash_moveout(pf,
2713 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2714 if (ret && (ret != -ENOENT))
2715 return ret;
2716
2717 ret = ice_hash_moveout(pf,
2718 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2719 if (ret && (ret != -ENOENT))
2720 return ret;
2721
2722 break;
2723 case ICE_HASH_GTPU_CTX_UP_IP:
2724 ret = ice_hash_remove(pf,
2725 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2726 if (ret && (ret != -ENOENT))
2727 return ret;
2728
2729 ret = ice_hash_remove(pf,
2730 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2731 if (ret && (ret != -ENOENT))
2732 return ret;
2733
2734 ret = ice_hash_moveout(pf,
2735 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2736 if (ret && (ret != -ENOENT))
2737 return ret;
2738
2739 ret = ice_hash_moveout(pf,
2740 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2741 if (ret && (ret != -ENOENT))
2742 return ret;
2743
2744 ret = ice_hash_moveout(pf,
2745 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2746 if (ret && (ret != -ENOENT))
2747 return ret;
2748
2749 break;
2750 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2751 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2752 ret = ice_hash_moveout(pf,
2753 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2754 if (ret && (ret != -ENOENT))
2755 return ret;
2756
2757 ret = ice_hash_moveout(pf,
2758 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2759 if (ret && (ret != -ENOENT))
2760 return ret;
2761
2762 ret = ice_hash_moveout(pf,
2763 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2764 if (ret && (ret != -ENOENT))
2765 return ret;
2766
2767 break;
2768 case ICE_HASH_GTPU_CTX_DW_IP:
2769 ret = ice_hash_remove(pf,
2770 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2771 if (ret && (ret != -ENOENT))
2772 return ret;
2773
2774 ret = ice_hash_remove(pf,
2775 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2776 if (ret && (ret != -ENOENT))
2777 return ret;
2778
2779 ret = ice_hash_moveout(pf,
2780 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2781 if (ret && (ret != -ENOENT))
2782 return ret;
2783
2784 ret = ice_hash_moveout(pf,
2785 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2786 if (ret && (ret != -ENOENT))
2787 return ret;
2788
2789 ret = ice_hash_moveout(pf,
2790 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2791 if (ret && (ret != -ENOENT))
2792 return ret;
2793
2794 break;
2795 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2796 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2797 ret = ice_hash_moveout(pf,
2798 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2799 if (ret && (ret != -ENOENT))
2800 return ret;
2801
2802 ret = ice_hash_moveout(pf,
2803 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2804 if (ret && (ret != -ENOENT))
2805 return ret;
2806
2807 ret = ice_hash_moveout(pf,
2808 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2809 if (ret && (ret != -ENOENT))
2810 return ret;
2811
2812 break;
2813 default:
2814 break;
2815 }
2816
2817 return 0;
2818 }
2819
calc_gtpu_ctx_idx(uint32_t hdr)2820 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2821 {
2822 u8 eh_idx, ip_idx;
2823
2824 if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2825 eh_idx = 0;
2826 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2827 eh_idx = 1;
2828 else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2829 eh_idx = 2;
2830 else
2831 return ICE_HASH_GTPU_CTX_MAX;
2832
2833 ip_idx = 0;
2834 if (hdr & ICE_FLOW_SEG_HDR_UDP)
2835 ip_idx = 1;
2836 else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2837 ip_idx = 2;
2838
2839 if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2840 return eh_idx * 3 + ip_idx;
2841 else
2842 return ICE_HASH_GTPU_CTX_MAX;
2843 }
2844
2845 static int
ice_add_rss_cfg_pre(struct ice_pf * pf,uint32_t hdr)2846 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2847 {
2848 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2849
2850 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2851 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2852 gtpu_ctx_idx);
2853 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2854 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2855 gtpu_ctx_idx);
2856
2857 return 0;
2858 }
2859
2860 static int
ice_add_rss_cfg_post_gtpu(struct ice_pf * pf,struct ice_hash_gtpu_ctx * ctx,u8 ctx_idx,struct ice_rss_hash_cfg * cfg)2861 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2862 u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2863 {
2864 int ret;
2865
2866 if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2867 ctx->ctx[ctx_idx] = *cfg;
2868
2869 switch (ctx_idx) {
2870 case ICE_HASH_GTPU_CTX_EH_IP:
2871 break;
2872 case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2873 ret = ice_hash_moveback(pf,
2874 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2875 if (ret && (ret != -ENOENT))
2876 return ret;
2877
2878 ret = ice_hash_moveback(pf,
2879 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2880 if (ret && (ret != -ENOENT))
2881 return ret;
2882
2883 ret = ice_hash_moveback(pf,
2884 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2885 if (ret && (ret != -ENOENT))
2886 return ret;
2887
2888 ret = ice_hash_moveback(pf,
2889 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2890 if (ret && (ret != -ENOENT))
2891 return ret;
2892
2893 break;
2894 case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2895 ret = ice_hash_moveback(pf,
2896 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2897 if (ret && (ret != -ENOENT))
2898 return ret;
2899
2900 ret = ice_hash_moveback(pf,
2901 &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2902 if (ret && (ret != -ENOENT))
2903 return ret;
2904
2905 ret = ice_hash_moveback(pf,
2906 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2907 if (ret && (ret != -ENOENT))
2908 return ret;
2909
2910 ret = ice_hash_moveback(pf,
2911 &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2912 if (ret && (ret != -ENOENT))
2913 return ret;
2914
2915 break;
2916 case ICE_HASH_GTPU_CTX_UP_IP:
2917 case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2918 case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2919 case ICE_HASH_GTPU_CTX_DW_IP:
2920 case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2921 case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2922 ret = ice_hash_moveback(pf,
2923 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2924 if (ret && (ret != -ENOENT))
2925 return ret;
2926
2927 ret = ice_hash_moveback(pf,
2928 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2929 if (ret && (ret != -ENOENT))
2930 return ret;
2931
2932 ret = ice_hash_moveback(pf,
2933 &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2934 if (ret && (ret != -ENOENT))
2935 return ret;
2936
2937 break;
2938 default:
2939 break;
2940 }
2941
2942 return 0;
2943 }
2944
2945 static int
ice_add_rss_cfg_post(struct ice_pf * pf,struct ice_rss_hash_cfg * cfg)2946 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2947 {
2948 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2949
2950 if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2951 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2952 gtpu_ctx_idx, cfg);
2953 else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2954 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2955 gtpu_ctx_idx, cfg);
2956
2957 return 0;
2958 }
2959
2960 static void
ice_rem_rss_cfg_post(struct ice_pf * pf,uint32_t hdr)2961 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2962 {
2963 u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2964
2965 if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2966 return;
2967
2968 if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2969 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2970 else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2971 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2972 }
2973
2974 int
ice_rem_rss_cfg_wrap(struct ice_pf * pf,uint16_t vsi_id,struct ice_rss_hash_cfg * cfg)2975 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2976 struct ice_rss_hash_cfg *cfg)
2977 {
2978 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2979 int ret;
2980
2981 ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2982 if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2983 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2984
2985 ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2986
2987 return 0;
2988 }
2989
2990 int
ice_add_rss_cfg_wrap(struct ice_pf * pf,uint16_t vsi_id,struct ice_rss_hash_cfg * cfg)2991 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2992 struct ice_rss_hash_cfg *cfg)
2993 {
2994 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2995 int ret;
2996
2997 ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2998 if (ret)
2999 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
3000
3001 ret = ice_add_rss_cfg(hw, vsi_id, cfg);
3002 if (ret)
3003 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
3004
3005 ret = ice_add_rss_cfg_post(pf, cfg);
3006 if (ret)
3007 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
3008
3009 return 0;
3010 }
3011
3012 static void
ice_rss_hash_set(struct ice_pf * pf,uint64_t rss_hf)3013 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
3014 {
3015 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3016 struct ice_vsi *vsi = pf->main_vsi;
3017 struct ice_rss_hash_cfg cfg;
3018 int ret;
3019
3020 #define ICE_RSS_HF_ALL ( \
3021 RTE_ETH_RSS_IPV4 | \
3022 RTE_ETH_RSS_IPV6 | \
3023 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
3024 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
3025 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
3026 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
3027 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
3028 RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
3029
3030 ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
3031 if (ret)
3032 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
3033 __func__, ret);
3034
3035 cfg.symm = 0;
3036 cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
3037 /* Configure RSS for IPv4 with src/dst addr as input set */
3038 if (rss_hf & RTE_ETH_RSS_IPV4) {
3039 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3040 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3041 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3042 if (ret)
3043 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
3044 __func__, ret);
3045 }
3046
3047 /* Configure RSS for IPv6 with src/dst addr as input set */
3048 if (rss_hf & RTE_ETH_RSS_IPV6) {
3049 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3050 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3051 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3052 if (ret)
3053 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
3054 __func__, ret);
3055 }
3056
3057 /* Configure RSS for udp4 with src/dst addr and port as input set */
3058 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) {
3059 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
3060 ICE_FLOW_SEG_HDR_IPV_OTHER;
3061 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3062 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3063 if (ret)
3064 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
3065 __func__, ret);
3066 }
3067
3068 /* Configure RSS for udp6 with src/dst addr and port as input set */
3069 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) {
3070 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
3071 ICE_FLOW_SEG_HDR_IPV_OTHER;
3072 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3073 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3074 if (ret)
3075 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
3076 __func__, ret);
3077 }
3078
3079 /* Configure RSS for tcp4 with src/dst addr and port as input set */
3080 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) {
3081 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
3082 ICE_FLOW_SEG_HDR_IPV_OTHER;
3083 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3084 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3085 if (ret)
3086 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
3087 __func__, ret);
3088 }
3089
3090 /* Configure RSS for tcp6 with src/dst addr and port as input set */
3091 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) {
3092 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
3093 ICE_FLOW_SEG_HDR_IPV_OTHER;
3094 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3095 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3096 if (ret)
3097 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
3098 __func__, ret);
3099 }
3100
3101 /* Configure RSS for sctp4 with src/dst addr and port as input set */
3102 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_SCTP) {
3103 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
3104 ICE_FLOW_SEG_HDR_IPV_OTHER;
3105 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
3106 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3107 if (ret)
3108 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
3109 __func__, ret);
3110 }
3111
3112 /* Configure RSS for sctp6 with src/dst addr and port as input set */
3113 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_SCTP) {
3114 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
3115 ICE_FLOW_SEG_HDR_IPV_OTHER;
3116 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
3117 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3118 if (ret)
3119 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
3120 __func__, ret);
3121 }
3122
3123 if (rss_hf & RTE_ETH_RSS_IPV4) {
3124 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
3125 ICE_FLOW_SEG_HDR_IPV_OTHER;
3126 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
3127 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3128 if (ret)
3129 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
3130 __func__, ret);
3131 }
3132
3133 if (rss_hf & RTE_ETH_RSS_IPV6) {
3134 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
3135 ICE_FLOW_SEG_HDR_IPV_OTHER;
3136 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
3137 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3138 if (ret)
3139 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
3140 __func__, ret);
3141 }
3142
3143 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) {
3144 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3145 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3146 cfg.hash_flds = ICE_HASH_UDP_IPV4;
3147 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3148 if (ret)
3149 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
3150 __func__, ret);
3151 }
3152
3153 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) {
3154 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3155 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3156 cfg.hash_flds = ICE_HASH_UDP_IPV6;
3157 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3158 if (ret)
3159 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3160 __func__, ret);
3161 }
3162
3163 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) {
3164 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3165 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3166 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3167 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3168 if (ret)
3169 PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3170 __func__, ret);
3171 }
3172
3173 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) {
3174 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3175 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3176 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3177 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3178 if (ret)
3179 PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3180 __func__, ret);
3181 }
3182
3183 pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3184 }
3185
3186 static void
ice_get_default_rss_key(uint8_t * rss_key,uint32_t rss_key_size)3187 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3188 {
3189 static struct ice_aqc_get_set_rss_keys default_key;
3190 static bool default_key_done;
3191 uint8_t *key = (uint8_t *)&default_key;
3192 size_t i;
3193
3194 if (rss_key_size > sizeof(default_key)) {
3195 PMD_DRV_LOG(WARNING,
3196 "requested size %u is larger than default %zu, "
3197 "only %zu bytes are gotten for key\n",
3198 rss_key_size, sizeof(default_key),
3199 sizeof(default_key));
3200 }
3201
3202 if (!default_key_done) {
3203 /* Calculate the default hash key */
3204 for (i = 0; i < sizeof(default_key); i++)
3205 key[i] = (uint8_t)rte_rand();
3206 default_key_done = true;
3207 }
3208 rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3209 }
3210
ice_init_rss(struct ice_pf * pf)3211 static int ice_init_rss(struct ice_pf *pf)
3212 {
3213 struct ice_hw *hw = ICE_PF_TO_HW(pf);
3214 struct ice_vsi *vsi = pf->main_vsi;
3215 struct rte_eth_dev_data *dev_data = pf->dev_data;
3216 struct ice_aq_get_set_rss_lut_params lut_params;
3217 struct rte_eth_rss_conf *rss_conf;
3218 struct ice_aqc_get_set_rss_keys key;
3219 uint16_t i, nb_q;
3220 int ret = 0;
3221 bool is_safe_mode = pf->adapter->is_safe_mode;
3222 uint32_t reg;
3223
3224 rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3225 nb_q = dev_data->nb_rx_queues;
3226 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3227 vsi->rss_lut_size = pf->hash_lut_size;
3228
3229 if (nb_q == 0) {
3230 PMD_DRV_LOG(WARNING,
3231 "RSS is not supported as rx queues number is zero\n");
3232 return 0;
3233 }
3234
3235 if (is_safe_mode) {
3236 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3237 return 0;
3238 }
3239
3240 if (!vsi->rss_key) {
3241 vsi->rss_key = rte_zmalloc(NULL,
3242 vsi->rss_key_size, 0);
3243 if (vsi->rss_key == NULL) {
3244 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3245 return -ENOMEM;
3246 }
3247 }
3248 if (!vsi->rss_lut) {
3249 vsi->rss_lut = rte_zmalloc(NULL,
3250 vsi->rss_lut_size, 0);
3251 if (vsi->rss_lut == NULL) {
3252 PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3253 rte_free(vsi->rss_key);
3254 vsi->rss_key = NULL;
3255 return -ENOMEM;
3256 }
3257 }
3258 /* configure RSS key */
3259 if (!rss_conf->rss_key)
3260 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3261 else
3262 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3263 RTE_MIN(rss_conf->rss_key_len,
3264 vsi->rss_key_size));
3265
3266 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3267 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3268 if (ret)
3269 goto out;
3270
3271 /* init RSS LUT table */
3272 for (i = 0; i < vsi->rss_lut_size; i++)
3273 vsi->rss_lut[i] = i % nb_q;
3274
3275 lut_params.vsi_handle = vsi->idx;
3276 lut_params.lut_size = vsi->rss_lut_size;
3277 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3278 lut_params.lut = vsi->rss_lut;
3279 lut_params.global_lut_id = 0;
3280 ret = ice_aq_set_rss_lut(hw, &lut_params);
3281 if (ret)
3282 goto out;
3283
3284 /* Enable registers for symmetric_toeplitz function. */
3285 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3286 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3287 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3288 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3289
3290 /* RSS hash configuration */
3291 ice_rss_hash_set(pf, rss_conf->rss_hf);
3292
3293 return 0;
3294 out:
3295 rte_free(vsi->rss_key);
3296 vsi->rss_key = NULL;
3297 rte_free(vsi->rss_lut);
3298 vsi->rss_lut = NULL;
3299 return -EINVAL;
3300 }
3301
3302 static int
ice_dev_configure(struct rte_eth_dev * dev)3303 ice_dev_configure(struct rte_eth_dev *dev)
3304 {
3305 struct ice_adapter *ad =
3306 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3307 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308 int ret;
3309
3310 /* Initialize to TRUE. If any of Rx queues doesn't meet the
3311 * bulk allocation or vector Rx preconditions we will reset it.
3312 */
3313 ad->rx_bulk_alloc_allowed = true;
3314 ad->tx_simple_allowed = true;
3315
3316 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
3317 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
3318
3319 if (dev->data->nb_rx_queues) {
3320 ret = ice_init_rss(pf);
3321 if (ret) {
3322 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3323 return ret;
3324 }
3325 }
3326
3327 return 0;
3328 }
3329
3330 static void
__vsi_queues_bind_intr(struct ice_vsi * vsi,uint16_t msix_vect,int base_queue,int nb_queue)3331 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3332 int base_queue, int nb_queue)
3333 {
3334 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3335 uint32_t val, val_tx;
3336 int rx_low_latency, i;
3337
3338 rx_low_latency = vsi->adapter->devargs.rx_low_latency;
3339 for (i = 0; i < nb_queue; i++) {
3340 /*do actual bind*/
3341 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3342 (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3343 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3344 (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3345
3346 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3347 base_queue + i, msix_vect);
3348
3349 /* set ITR0 value */
3350 if (rx_low_latency) {
3351 /**
3352 * Empirical configuration for optimal real time
3353 * latency reduced interrupt throttling to 2us
3354 */
3355 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
3356 ICE_WRITE_REG(hw, QRX_ITR(base_queue + i),
3357 QRX_ITR_NO_EXPR_M);
3358 } else {
3359 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3360 ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), 0);
3361 }
3362
3363 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3364 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3365 }
3366 }
3367
3368 void
ice_vsi_queues_bind_intr(struct ice_vsi * vsi)3369 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3370 {
3371 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3372 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3373 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3374 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3375 uint16_t msix_vect = vsi->msix_intr;
3376 uint16_t nb_msix = RTE_MIN(vsi->nb_msix,
3377 rte_intr_nb_efd_get(intr_handle));
3378 uint16_t queue_idx = 0;
3379 int record = 0;
3380 int i;
3381
3382 /* clear Rx/Tx queue interrupt */
3383 for (i = 0; i < vsi->nb_used_qps; i++) {
3384 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3385 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3386 }
3387
3388 /* PF bind interrupt */
3389 if (rte_intr_dp_is_en(intr_handle)) {
3390 queue_idx = 0;
3391 record = 1;
3392 }
3393
3394 for (i = 0; i < vsi->nb_used_qps; i++) {
3395 if (nb_msix <= 1) {
3396 if (!rte_intr_allow_others(intr_handle))
3397 msix_vect = ICE_MISC_VEC_ID;
3398
3399 /* uio mapping all queue to one msix_vect */
3400 __vsi_queues_bind_intr(vsi, msix_vect,
3401 vsi->base_queue + i,
3402 vsi->nb_used_qps - i);
3403
3404 for (; !!record && i < vsi->nb_used_qps; i++)
3405 rte_intr_vec_list_index_set(intr_handle,
3406 queue_idx + i, msix_vect);
3407
3408 break;
3409 }
3410
3411 /* vfio 1:1 queue/msix_vect mapping */
3412 __vsi_queues_bind_intr(vsi, msix_vect,
3413 vsi->base_queue + i, 1);
3414
3415 if (!!record)
3416 rte_intr_vec_list_index_set(intr_handle,
3417 queue_idx + i,
3418 msix_vect);
3419
3420 msix_vect++;
3421 nb_msix--;
3422 }
3423 }
3424
3425 void
ice_vsi_enable_queues_intr(struct ice_vsi * vsi)3426 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3427 {
3428 struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3429 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3430 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3431 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3432 uint16_t msix_intr, i;
3433
3434 if (rte_intr_allow_others(intr_handle))
3435 for (i = 0; i < vsi->nb_used_qps; i++) {
3436 msix_intr = vsi->msix_intr + i;
3437 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3438 GLINT_DYN_CTL_INTENA_M |
3439 GLINT_DYN_CTL_CLEARPBA_M |
3440 GLINT_DYN_CTL_ITR_INDX_M |
3441 GLINT_DYN_CTL_WB_ON_ITR_M);
3442 }
3443 else
3444 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3445 GLINT_DYN_CTL_INTENA_M |
3446 GLINT_DYN_CTL_CLEARPBA_M |
3447 GLINT_DYN_CTL_ITR_INDX_M |
3448 GLINT_DYN_CTL_WB_ON_ITR_M);
3449 }
3450
3451 static int
ice_rxq_intr_setup(struct rte_eth_dev * dev)3452 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3453 {
3454 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3455 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3456 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3457 struct ice_vsi *vsi = pf->main_vsi;
3458 uint32_t intr_vector = 0;
3459
3460 rte_intr_disable(intr_handle);
3461
3462 /* check and configure queue intr-vector mapping */
3463 if ((rte_intr_cap_multiple(intr_handle) ||
3464 !RTE_ETH_DEV_SRIOV(dev).active) &&
3465 dev->data->dev_conf.intr_conf.rxq != 0) {
3466 intr_vector = dev->data->nb_rx_queues;
3467 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3468 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3469 ICE_MAX_INTR_QUEUE_NUM);
3470 return -ENOTSUP;
3471 }
3472 if (rte_intr_efd_enable(intr_handle, intr_vector))
3473 return -1;
3474 }
3475
3476 if (rte_intr_dp_is_en(intr_handle)) {
3477 if (rte_intr_vec_list_alloc(intr_handle, NULL,
3478 dev->data->nb_rx_queues)) {
3479 PMD_DRV_LOG(ERR,
3480 "Failed to allocate %d rx_queues intr_vec",
3481 dev->data->nb_rx_queues);
3482 return -ENOMEM;
3483 }
3484 }
3485
3486 /* Map queues with MSIX interrupt */
3487 vsi->nb_used_qps = dev->data->nb_rx_queues;
3488 ice_vsi_queues_bind_intr(vsi);
3489
3490 /* Enable interrupts for all the queues */
3491 ice_vsi_enable_queues_intr(vsi);
3492
3493 rte_intr_enable(intr_handle);
3494
3495 return 0;
3496 }
3497
3498 static void
ice_get_init_link_status(struct rte_eth_dev * dev)3499 ice_get_init_link_status(struct rte_eth_dev *dev)
3500 {
3501 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3502 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3503 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3504 struct ice_link_status link_status;
3505 int ret;
3506
3507 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3508 &link_status, NULL);
3509 if (ret != ICE_SUCCESS) {
3510 PMD_DRV_LOG(ERR, "Failed to get link info");
3511 pf->init_link_up = false;
3512 return;
3513 }
3514
3515 if (link_status.link_info & ICE_AQ_LINK_UP)
3516 pf->init_link_up = true;
3517 }
3518
3519 static int
ice_pps_out_cfg(struct ice_hw * hw,int idx,int timer)3520 ice_pps_out_cfg(struct ice_hw *hw, int idx, int timer)
3521 {
3522 uint64_t current_time, start_time;
3523 uint32_t hi, lo, lo2, func, val;
3524
3525 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3526 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3527 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3528
3529 if (lo2 < lo) {
3530 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(timer));
3531 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(timer));
3532 }
3533
3534 current_time = ((uint64_t)hi << 32) | lo;
3535
3536 start_time = (current_time + NSEC_PER_SEC) /
3537 NSEC_PER_SEC * NSEC_PER_SEC;
3538 start_time = start_time - PPS_OUT_DELAY_NS;
3539
3540 func = 8 + idx + timer * 4;
3541 val = GLGEN_GPIO_CTL_PIN_DIR_M |
3542 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
3543 GLGEN_GPIO_CTL_PIN_FUNC_M);
3544
3545 /* Write clkout with half of period value */
3546 ICE_WRITE_REG(hw, GLTSYN_CLKO(idx, timer), NSEC_PER_SEC / 2);
3547
3548 /* Write TARGET time register */
3549 ICE_WRITE_REG(hw, GLTSYN_TGT_L(idx, timer), start_time & 0xffffffff);
3550 ICE_WRITE_REG(hw, GLTSYN_TGT_H(idx, timer), start_time >> 32);
3551
3552 /* Write AUX_OUT register */
3553 ICE_WRITE_REG(hw, GLTSYN_AUX_OUT(idx, timer),
3554 GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M);
3555
3556 /* Write GPIO CTL register */
3557 ICE_WRITE_REG(hw, GLGEN_GPIO_CTL(idx), val);
3558
3559 return 0;
3560 }
3561
3562 static int
ice_dev_start(struct rte_eth_dev * dev)3563 ice_dev_start(struct rte_eth_dev *dev)
3564 {
3565 struct rte_eth_dev_data *data = dev->data;
3566 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3568 struct ice_vsi *vsi = pf->main_vsi;
3569 struct ice_adapter *ad =
3570 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3571 uint16_t nb_rxq = 0;
3572 uint16_t nb_txq, i;
3573 uint16_t max_frame_size;
3574 int mask, ret;
3575 uint8_t timer = hw->func_caps.ts_func_info.tmr_index_owned;
3576 uint32_t pin_idx = ad->devargs.pin_idx;
3577
3578 /* program Tx queues' context in hardware */
3579 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3580 ret = ice_tx_queue_start(dev, nb_txq);
3581 if (ret) {
3582 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3583 goto tx_err;
3584 }
3585 }
3586
3587 /* program Rx queues' context in hardware*/
3588 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3589 ret = ice_rx_queue_start(dev, nb_rxq);
3590 if (ret) {
3591 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3592 goto rx_err;
3593 }
3594 }
3595
3596 ice_set_rx_function(dev);
3597 ice_set_tx_function(dev);
3598
3599 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
3600 RTE_ETH_VLAN_EXTEND_MASK;
3601 ret = ice_vlan_offload_set(dev, mask);
3602 if (ret) {
3603 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3604 goto rx_err;
3605 }
3606
3607 /* enable Rx interrupt and mapping Rx queue to interrupt vector */
3608 if (ice_rxq_intr_setup(dev))
3609 return -EIO;
3610
3611 /* Enable receiving broadcast packets and transmitting packets */
3612 ret = ice_set_vsi_promisc(hw, vsi->idx,
3613 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3614 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3615 0);
3616 if (ret != ICE_SUCCESS)
3617 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3618
3619 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3620 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3621 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3622 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3623 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3624 ICE_AQ_LINK_EVENT_AN_COMPLETED |
3625 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3626 NULL);
3627 if (ret != ICE_SUCCESS)
3628 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3629
3630 ice_get_init_link_status(dev);
3631
3632 ice_dev_set_link_up(dev);
3633
3634 /* Call get_link_info aq command to enable/disable LSE */
3635 ice_link_update(dev, 1);
3636
3637 pf->adapter_stopped = false;
3638
3639 /* Set the max frame size to default value*/
3640 max_frame_size = pf->dev_data->mtu ?
3641 pf->dev_data->mtu + ICE_ETH_OVERHEAD :
3642 ICE_FRAME_SIZE_MAX;
3643
3644 /* Set the max frame size to HW*/
3645 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3646
3647 if (ad->devargs.pps_out_ena) {
3648 ret = ice_pps_out_cfg(hw, pin_idx, timer);
3649 if (ret) {
3650 PMD_DRV_LOG(ERR, "Fail to configure 1pps out");
3651 goto rx_err;
3652 }
3653 }
3654
3655 return 0;
3656
3657 /* stop the started queues if failed to start all queues */
3658 rx_err:
3659 for (i = 0; i < nb_rxq; i++)
3660 ice_rx_queue_stop(dev, i);
3661 tx_err:
3662 for (i = 0; i < nb_txq; i++)
3663 ice_tx_queue_stop(dev, i);
3664
3665 return -EIO;
3666 }
3667
3668 static int
ice_dev_reset(struct rte_eth_dev * dev)3669 ice_dev_reset(struct rte_eth_dev *dev)
3670 {
3671 int ret;
3672
3673 if (dev->data->sriov.active)
3674 return -ENOTSUP;
3675
3676 ret = ice_dev_uninit(dev);
3677 if (ret) {
3678 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3679 return -ENXIO;
3680 }
3681
3682 ret = ice_dev_init(dev);
3683 if (ret) {
3684 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3685 return -ENXIO;
3686 }
3687
3688 return 0;
3689 }
3690
3691 static int
ice_dev_info_get(struct rte_eth_dev * dev,struct rte_eth_dev_info * dev_info)3692 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3693 {
3694 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3695 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696 struct ice_vsi *vsi = pf->main_vsi;
3697 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3698 bool is_safe_mode = pf->adapter->is_safe_mode;
3699 u64 phy_type_low;
3700 u64 phy_type_high;
3701
3702 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3703 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3704 dev_info->max_rx_queues = vsi->nb_qps;
3705 dev_info->max_tx_queues = vsi->nb_qps;
3706 dev_info->max_mac_addrs = vsi->max_macaddrs;
3707 dev_info->max_vfs = pci_dev->max_vfs;
3708 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3709 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3710
3711 dev_info->rx_offload_capa =
3712 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
3713 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
3714 RTE_ETH_RX_OFFLOAD_SCATTER |
3715 RTE_ETH_RX_OFFLOAD_VLAN_FILTER;
3716 dev_info->tx_offload_capa =
3717 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
3718 RTE_ETH_TX_OFFLOAD_TCP_TSO |
3719 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
3720 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
3721 dev_info->flow_type_rss_offloads = 0;
3722
3723 if (!is_safe_mode) {
3724 dev_info->rx_offload_capa |=
3725 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
3726 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
3727 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
3728 RTE_ETH_RX_OFFLOAD_QINQ_STRIP |
3729 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3730 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
3731 RTE_ETH_RX_OFFLOAD_RSS_HASH |
3732 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
3733 dev_info->tx_offload_capa |=
3734 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
3735 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
3736 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
3737 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
3738 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
3739 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3740 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
3741 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3742 }
3743
3744 dev_info->rx_queue_offload_capa = 0;
3745 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
3746
3747 dev_info->reta_size = pf->hash_lut_size;
3748 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3749
3750 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3751 .rx_thresh = {
3752 .pthresh = ICE_DEFAULT_RX_PTHRESH,
3753 .hthresh = ICE_DEFAULT_RX_HTHRESH,
3754 .wthresh = ICE_DEFAULT_RX_WTHRESH,
3755 },
3756 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3757 .rx_drop_en = 0,
3758 .offloads = 0,
3759 };
3760
3761 dev_info->default_txconf = (struct rte_eth_txconf) {
3762 .tx_thresh = {
3763 .pthresh = ICE_DEFAULT_TX_PTHRESH,
3764 .hthresh = ICE_DEFAULT_TX_HTHRESH,
3765 .wthresh = ICE_DEFAULT_TX_WTHRESH,
3766 },
3767 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3768 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3769 .offloads = 0,
3770 };
3771
3772 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3773 .nb_max = ICE_MAX_RING_DESC,
3774 .nb_min = ICE_MIN_RING_DESC,
3775 .nb_align = ICE_ALIGN_RING_DESC,
3776 };
3777
3778 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3779 .nb_max = ICE_MAX_RING_DESC,
3780 .nb_min = ICE_MIN_RING_DESC,
3781 .nb_align = ICE_ALIGN_RING_DESC,
3782 };
3783
3784 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M |
3785 RTE_ETH_LINK_SPEED_100M |
3786 RTE_ETH_LINK_SPEED_1G |
3787 RTE_ETH_LINK_SPEED_2_5G |
3788 RTE_ETH_LINK_SPEED_5G |
3789 RTE_ETH_LINK_SPEED_10G |
3790 RTE_ETH_LINK_SPEED_20G |
3791 RTE_ETH_LINK_SPEED_25G;
3792
3793 phy_type_low = hw->port_info->phy.phy_type_low;
3794 phy_type_high = hw->port_info->phy.phy_type_high;
3795
3796 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3797 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_50G;
3798
3799 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3800 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3801 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100G;
3802
3803 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3804 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3805
3806 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3807 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3808 dev_info->default_rxportconf.nb_queues = 1;
3809 dev_info->default_txportconf.nb_queues = 1;
3810 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3811 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3812
3813 return 0;
3814 }
3815
3816 static inline int
ice_atomic_read_link_status(struct rte_eth_dev * dev,struct rte_eth_link * link)3817 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3818 struct rte_eth_link *link)
3819 {
3820 struct rte_eth_link *dst = link;
3821 struct rte_eth_link *src = &dev->data->dev_link;
3822
3823 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3824 *(uint64_t *)src) == 0)
3825 return -1;
3826
3827 return 0;
3828 }
3829
3830 static inline int
ice_atomic_write_link_status(struct rte_eth_dev * dev,struct rte_eth_link * link)3831 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3832 struct rte_eth_link *link)
3833 {
3834 struct rte_eth_link *dst = &dev->data->dev_link;
3835 struct rte_eth_link *src = link;
3836
3837 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3838 *(uint64_t *)src) == 0)
3839 return -1;
3840
3841 return 0;
3842 }
3843
3844 static int
ice_link_update(struct rte_eth_dev * dev,int wait_to_complete)3845 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3846 {
3847 #define CHECK_INTERVAL 100 /* 100ms */
3848 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3849 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850 struct ice_link_status link_status;
3851 struct rte_eth_link link, old;
3852 int status;
3853 unsigned int rep_cnt = MAX_REPEAT_TIME;
3854 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3855
3856 memset(&link, 0, sizeof(link));
3857 memset(&old, 0, sizeof(old));
3858 memset(&link_status, 0, sizeof(link_status));
3859 ice_atomic_read_link_status(dev, &old);
3860
3861 do {
3862 /* Get link status information from hardware */
3863 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3864 &link_status, NULL);
3865 if (status != ICE_SUCCESS) {
3866 link.link_speed = RTE_ETH_SPEED_NUM_100M;
3867 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3868 PMD_DRV_LOG(ERR, "Failed to get link info");
3869 goto out;
3870 }
3871
3872 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3873 if (!wait_to_complete || link.link_status)
3874 break;
3875
3876 rte_delay_ms(CHECK_INTERVAL);
3877 } while (--rep_cnt);
3878
3879 if (!link.link_status)
3880 goto out;
3881
3882 /* Full-duplex operation at all supported speeds */
3883 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3884
3885 /* Parse the link status */
3886 switch (link_status.link_speed) {
3887 case ICE_AQ_LINK_SPEED_10MB:
3888 link.link_speed = RTE_ETH_SPEED_NUM_10M;
3889 break;
3890 case ICE_AQ_LINK_SPEED_100MB:
3891 link.link_speed = RTE_ETH_SPEED_NUM_100M;
3892 break;
3893 case ICE_AQ_LINK_SPEED_1000MB:
3894 link.link_speed = RTE_ETH_SPEED_NUM_1G;
3895 break;
3896 case ICE_AQ_LINK_SPEED_2500MB:
3897 link.link_speed = RTE_ETH_SPEED_NUM_2_5G;
3898 break;
3899 case ICE_AQ_LINK_SPEED_5GB:
3900 link.link_speed = RTE_ETH_SPEED_NUM_5G;
3901 break;
3902 case ICE_AQ_LINK_SPEED_10GB:
3903 link.link_speed = RTE_ETH_SPEED_NUM_10G;
3904 break;
3905 case ICE_AQ_LINK_SPEED_20GB:
3906 link.link_speed = RTE_ETH_SPEED_NUM_20G;
3907 break;
3908 case ICE_AQ_LINK_SPEED_25GB:
3909 link.link_speed = RTE_ETH_SPEED_NUM_25G;
3910 break;
3911 case ICE_AQ_LINK_SPEED_40GB:
3912 link.link_speed = RTE_ETH_SPEED_NUM_40G;
3913 break;
3914 case ICE_AQ_LINK_SPEED_50GB:
3915 link.link_speed = RTE_ETH_SPEED_NUM_50G;
3916 break;
3917 case ICE_AQ_LINK_SPEED_100GB:
3918 link.link_speed = RTE_ETH_SPEED_NUM_100G;
3919 break;
3920 case ICE_AQ_LINK_SPEED_UNKNOWN:
3921 PMD_DRV_LOG(ERR, "Unknown link speed");
3922 link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
3923 break;
3924 default:
3925 PMD_DRV_LOG(ERR, "None link speed");
3926 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
3927 break;
3928 }
3929
3930 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3931 RTE_ETH_LINK_SPEED_FIXED);
3932
3933 out:
3934 ice_atomic_write_link_status(dev, &link);
3935 if (link.link_status == old.link_status)
3936 return -1;
3937
3938 return 0;
3939 }
3940
3941 /* Force the physical link state by getting the current PHY capabilities from
3942 * hardware and setting the PHY config based on the determined capabilities. If
3943 * link changes, link event will be triggered because both the Enable Automatic
3944 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3945 */
3946 static enum ice_status
ice_force_phys_link_state(struct ice_hw * hw,bool link_up)3947 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3948 {
3949 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3950 struct ice_aqc_get_phy_caps_data *pcaps;
3951 struct ice_port_info *pi;
3952 enum ice_status status;
3953
3954 if (!hw || !hw->port_info)
3955 return ICE_ERR_PARAM;
3956
3957 pi = hw->port_info;
3958
3959 pcaps = (struct ice_aqc_get_phy_caps_data *)
3960 ice_malloc(hw, sizeof(*pcaps));
3961 if (!pcaps)
3962 return ICE_ERR_NO_MEMORY;
3963
3964 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3965 pcaps, NULL);
3966 if (status)
3967 goto out;
3968
3969 /* No change in link */
3970 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3971 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3972 goto out;
3973
3974 cfg.phy_type_low = pcaps->phy_type_low;
3975 cfg.phy_type_high = pcaps->phy_type_high;
3976 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3977 cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3978 cfg.eee_cap = pcaps->eee_cap;
3979 cfg.eeer_value = pcaps->eeer_value;
3980 cfg.link_fec_opt = pcaps->link_fec_options;
3981 if (link_up)
3982 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3983 else
3984 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3985
3986 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3987
3988 out:
3989 ice_free(hw, pcaps);
3990 return status;
3991 }
3992
3993 static int
ice_dev_set_link_up(struct rte_eth_dev * dev)3994 ice_dev_set_link_up(struct rte_eth_dev *dev)
3995 {
3996 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997
3998 return ice_force_phys_link_state(hw, true);
3999 }
4000
4001 static int
ice_dev_set_link_down(struct rte_eth_dev * dev)4002 ice_dev_set_link_down(struct rte_eth_dev *dev)
4003 {
4004 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005
4006 return ice_force_phys_link_state(hw, false);
4007 }
4008
4009 static int
ice_mtu_set(struct rte_eth_dev * dev,uint16_t mtu __rte_unused)4010 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused)
4011 {
4012 /* mtu setting is forbidden if port is start */
4013 if (dev->data->dev_started != 0) {
4014 PMD_DRV_LOG(ERR,
4015 "port %d must be stopped before configuration",
4016 dev->data->port_id);
4017 return -EBUSY;
4018 }
4019
4020 return 0;
4021 }
4022
ice_macaddr_set(struct rte_eth_dev * dev,struct rte_ether_addr * mac_addr)4023 static int ice_macaddr_set(struct rte_eth_dev *dev,
4024 struct rte_ether_addr *mac_addr)
4025 {
4026 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4027 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4028 struct ice_vsi *vsi = pf->main_vsi;
4029 struct ice_mac_filter *f;
4030 uint8_t flags = 0;
4031 int ret;
4032
4033 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
4034 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
4035 return -EINVAL;
4036 }
4037
4038 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4039 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
4040 break;
4041 }
4042
4043 if (!f) {
4044 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
4045 return -EIO;
4046 }
4047
4048 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
4049 if (ret != ICE_SUCCESS) {
4050 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
4051 return -EIO;
4052 }
4053 ret = ice_add_mac_filter(vsi, mac_addr);
4054 if (ret != ICE_SUCCESS) {
4055 PMD_DRV_LOG(ERR, "Failed to add mac filter");
4056 return -EIO;
4057 }
4058 rte_ether_addr_copy(mac_addr, &pf->dev_addr);
4059
4060 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
4061 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
4062 if (ret != ICE_SUCCESS)
4063 PMD_DRV_LOG(ERR, "Failed to set manage mac");
4064
4065 return 0;
4066 }
4067
4068 /* Add a MAC address, and update filters */
4069 static int
ice_macaddr_add(struct rte_eth_dev * dev,struct rte_ether_addr * mac_addr,__rte_unused uint32_t index,__rte_unused uint32_t pool)4070 ice_macaddr_add(struct rte_eth_dev *dev,
4071 struct rte_ether_addr *mac_addr,
4072 __rte_unused uint32_t index,
4073 __rte_unused uint32_t pool)
4074 {
4075 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4076 struct ice_vsi *vsi = pf->main_vsi;
4077 int ret;
4078
4079 ret = ice_add_mac_filter(vsi, mac_addr);
4080 if (ret != ICE_SUCCESS) {
4081 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
4082 return -EINVAL;
4083 }
4084
4085 return ICE_SUCCESS;
4086 }
4087
4088 /* Remove a MAC address, and update filters */
4089 static void
ice_macaddr_remove(struct rte_eth_dev * dev,uint32_t index)4090 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4091 {
4092 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4093 struct ice_vsi *vsi = pf->main_vsi;
4094 struct rte_eth_dev_data *data = dev->data;
4095 struct rte_ether_addr *macaddr;
4096 int ret;
4097
4098 macaddr = &data->mac_addrs[index];
4099 ret = ice_remove_mac_filter(vsi, macaddr);
4100 if (ret) {
4101 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
4102 return;
4103 }
4104 }
4105
4106 static int
ice_vlan_filter_set(struct rte_eth_dev * dev,uint16_t vlan_id,int on)4107 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4108 {
4109 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4110 struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
4111 struct ice_vsi *vsi = pf->main_vsi;
4112 int ret;
4113
4114 PMD_INIT_FUNC_TRACE();
4115
4116 /**
4117 * Vlan 0 is the generic filter for untagged packets
4118 * and can't be removed or added by user.
4119 */
4120 if (vlan_id == 0)
4121 return 0;
4122
4123 if (on) {
4124 ret = ice_add_vlan_filter(vsi, &vlan);
4125 if (ret < 0) {
4126 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
4127 return -EINVAL;
4128 }
4129 } else {
4130 ret = ice_remove_vlan_filter(vsi, &vlan);
4131 if (ret < 0) {
4132 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
4133 return -EINVAL;
4134 }
4135 }
4136
4137 return 0;
4138 }
4139
4140 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
4141 * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
4142 * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
4143 * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
4144 *
4145 * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
4146 * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
4147 * traffic in SVM, since the VLAN TPID isn't part of filtering.
4148 *
4149 * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
4150 * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
4151 * part of filtering.
4152 */
4153 static int
ice_vsi_add_vlan_zero(struct ice_vsi * vsi)4154 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
4155 {
4156 struct ice_vlan vlan;
4157 int err;
4158
4159 vlan = ICE_VLAN(0, 0);
4160 err = ice_add_vlan_filter(vsi, &vlan);
4161 if (err) {
4162 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
4163 return err;
4164 }
4165
4166 /* in SVM both VLAN 0 filters are identical */
4167 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4168 return 0;
4169
4170 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4171 err = ice_add_vlan_filter(vsi, &vlan);
4172 if (err) {
4173 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
4174 return err;
4175 }
4176
4177 return 0;
4178 }
4179
4180 /*
4181 * Delete the VLAN 0 filters in the same manner that they were added in
4182 * ice_vsi_add_vlan_zero.
4183 */
4184 static int
ice_vsi_del_vlan_zero(struct ice_vsi * vsi)4185 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
4186 {
4187 struct ice_vlan vlan;
4188 int err;
4189
4190 vlan = ICE_VLAN(0, 0);
4191 err = ice_remove_vlan_filter(vsi, &vlan);
4192 if (err) {
4193 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
4194 return err;
4195 }
4196
4197 /* in SVM both VLAN 0 filters are identical */
4198 if (!ice_is_dvm_ena(&vsi->adapter->hw))
4199 return 0;
4200
4201 vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
4202 err = ice_remove_vlan_filter(vsi, &vlan);
4203 if (err) {
4204 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4205 return err;
4206 }
4207
4208 return 0;
4209 }
4210
4211 /* Configure vlan filter on or off */
4212 static int
ice_vsi_config_vlan_filter(struct ice_vsi * vsi,bool on)4213 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4214 {
4215 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4216 struct ice_vsi_ctx ctxt;
4217 uint8_t sw_flags2;
4218 int ret = 0;
4219
4220 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4221
4222 if (on)
4223 vsi->info.sw_flags2 |= sw_flags2;
4224 else
4225 vsi->info.sw_flags2 &= ~sw_flags2;
4226
4227 vsi->info.sw_id = hw->port_info->sw_id;
4228 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4229 ctxt.info.valid_sections =
4230 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4231 ICE_AQ_VSI_PROP_SECURITY_VALID);
4232 ctxt.vsi_num = vsi->vsi_id;
4233
4234 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4235 if (ret) {
4236 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4237 on ? "enable" : "disable");
4238 return -EINVAL;
4239 } else {
4240 vsi->info.valid_sections |=
4241 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4242 ICE_AQ_VSI_PROP_SECURITY_VALID);
4243 }
4244
4245 /* consist with other drivers, allow untagged packet when vlan filter on */
4246 if (on)
4247 ret = ice_vsi_add_vlan_zero(vsi);
4248 else
4249 ret = ice_vsi_del_vlan_zero(vsi);
4250
4251 return 0;
4252 }
4253
4254 /* Manage VLAN stripping for the VSI for Rx */
4255 static int
ice_vsi_manage_vlan_stripping(struct ice_vsi * vsi,bool ena)4256 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4257 {
4258 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4259 struct ice_vsi_ctx ctxt;
4260 enum ice_status status;
4261 int err = 0;
4262
4263 /* do not allow modifying VLAN stripping when a port VLAN is configured
4264 * on this VSI
4265 */
4266 if (vsi->info.port_based_inner_vlan)
4267 return 0;
4268
4269 memset(&ctxt, 0, sizeof(ctxt));
4270
4271 if (ena)
4272 /* Strip VLAN tag from Rx packet and put it in the desc */
4273 ctxt.info.inner_vlan_flags =
4274 ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4275 else
4276 /* Disable stripping. Leave tag in packet */
4277 ctxt.info.inner_vlan_flags =
4278 ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4279
4280 /* Allow all packets untagged/tagged */
4281 ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4282
4283 ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4284
4285 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4286 if (status) {
4287 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4288 ena ? "enable" : "disable");
4289 err = -EIO;
4290 } else {
4291 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4292 }
4293
4294 return err;
4295 }
4296
4297 static int
ice_vsi_ena_inner_stripping(struct ice_vsi * vsi)4298 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4299 {
4300 return ice_vsi_manage_vlan_stripping(vsi, true);
4301 }
4302
4303 static int
ice_vsi_dis_inner_stripping(struct ice_vsi * vsi)4304 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4305 {
4306 return ice_vsi_manage_vlan_stripping(vsi, false);
4307 }
4308
ice_vsi_ena_outer_stripping(struct ice_vsi * vsi)4309 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4310 {
4311 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4312 struct ice_vsi_ctx ctxt;
4313 enum ice_status status;
4314 int err = 0;
4315
4316 /* do not allow modifying VLAN stripping when a port VLAN is configured
4317 * on this VSI
4318 */
4319 if (vsi->info.port_based_outer_vlan)
4320 return 0;
4321
4322 memset(&ctxt, 0, sizeof(ctxt));
4323
4324 ctxt.info.valid_sections =
4325 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4326 /* clear current outer VLAN strip settings */
4327 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4328 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4329 ctxt.info.outer_vlan_flags |=
4330 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4331 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4332 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4333 ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4334
4335 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4336 if (status) {
4337 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4338 err = -EIO;
4339 } else {
4340 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4341 }
4342
4343 return err;
4344 }
4345
4346 static int
ice_vsi_dis_outer_stripping(struct ice_vsi * vsi)4347 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4348 {
4349 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4350 struct ice_vsi_ctx ctxt;
4351 enum ice_status status;
4352 int err = 0;
4353
4354 if (vsi->info.port_based_outer_vlan)
4355 return 0;
4356
4357 memset(&ctxt, 0, sizeof(ctxt));
4358
4359 ctxt.info.valid_sections =
4360 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4361 /* clear current outer VLAN strip settings */
4362 ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4363 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4364 ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4365 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4366
4367 status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4368 if (status) {
4369 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4370 err = -EIO;
4371 } else {
4372 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4373 }
4374
4375 return err;
4376 }
4377
4378 static int
ice_vsi_config_vlan_stripping(struct ice_vsi * vsi,bool ena)4379 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4380 {
4381 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4382 int ret;
4383
4384 if (ice_is_dvm_ena(hw)) {
4385 if (ena)
4386 ret = ice_vsi_ena_outer_stripping(vsi);
4387 else
4388 ret = ice_vsi_dis_outer_stripping(vsi);
4389 } else {
4390 if (ena)
4391 ret = ice_vsi_ena_inner_stripping(vsi);
4392 else
4393 ret = ice_vsi_dis_inner_stripping(vsi);
4394 }
4395
4396 return ret;
4397 }
4398
4399 static int
ice_vlan_offload_set(struct rte_eth_dev * dev,int mask)4400 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4401 {
4402 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4403 struct ice_vsi *vsi = pf->main_vsi;
4404 struct rte_eth_rxmode *rxmode;
4405
4406 rxmode = &dev->data->dev_conf.rxmode;
4407 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
4408 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
4409 ice_vsi_config_vlan_filter(vsi, true);
4410 else
4411 ice_vsi_config_vlan_filter(vsi, false);
4412 }
4413
4414 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
4415 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
4416 ice_vsi_config_vlan_stripping(vsi, true);
4417 else
4418 ice_vsi_config_vlan_stripping(vsi, false);
4419 }
4420
4421 return 0;
4422 }
4423
4424 static int
ice_get_rss_lut(struct ice_vsi * vsi,uint8_t * lut,uint16_t lut_size)4425 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4426 {
4427 struct ice_aq_get_set_rss_lut_params lut_params;
4428 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4429 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4430 int ret;
4431
4432 if (!lut)
4433 return -EINVAL;
4434
4435 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4436 lut_params.vsi_handle = vsi->idx;
4437 lut_params.lut_size = lut_size;
4438 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4439 lut_params.lut = lut;
4440 lut_params.global_lut_id = 0;
4441 ret = ice_aq_get_rss_lut(hw, &lut_params);
4442 if (ret) {
4443 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4444 return -EINVAL;
4445 }
4446 } else {
4447 uint64_t *lut_dw = (uint64_t *)lut;
4448 uint16_t i, lut_size_dw = lut_size / 4;
4449
4450 for (i = 0; i < lut_size_dw; i++)
4451 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4452 }
4453
4454 return 0;
4455 }
4456
4457 static int
ice_set_rss_lut(struct ice_vsi * vsi,uint8_t * lut,uint16_t lut_size)4458 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4459 {
4460 struct ice_aq_get_set_rss_lut_params lut_params;
4461 struct ice_pf *pf;
4462 struct ice_hw *hw;
4463 int ret;
4464
4465 if (!vsi || !lut)
4466 return -EINVAL;
4467
4468 pf = ICE_VSI_TO_PF(vsi);
4469 hw = ICE_VSI_TO_HW(vsi);
4470
4471 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4472 lut_params.vsi_handle = vsi->idx;
4473 lut_params.lut_size = lut_size;
4474 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4475 lut_params.lut = lut;
4476 lut_params.global_lut_id = 0;
4477 ret = ice_aq_set_rss_lut(hw, &lut_params);
4478 if (ret) {
4479 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4480 return -EINVAL;
4481 }
4482 } else {
4483 uint64_t *lut_dw = (uint64_t *)lut;
4484 uint16_t i, lut_size_dw = lut_size / 4;
4485
4486 for (i = 0; i < lut_size_dw; i++)
4487 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4488
4489 ice_flush(hw);
4490 }
4491
4492 return 0;
4493 }
4494
4495 static int
ice_rss_reta_update(struct rte_eth_dev * dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)4496 ice_rss_reta_update(struct rte_eth_dev *dev,
4497 struct rte_eth_rss_reta_entry64 *reta_conf,
4498 uint16_t reta_size)
4499 {
4500 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4501 uint16_t i, lut_size = pf->hash_lut_size;
4502 uint16_t idx, shift;
4503 uint8_t *lut;
4504 int ret;
4505
4506 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4507 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4508 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4509 PMD_DRV_LOG(ERR,
4510 "The size of hash lookup table configured (%d)"
4511 "doesn't match the number hardware can "
4512 "supported (128, 512, 2048)",
4513 reta_size);
4514 return -EINVAL;
4515 }
4516
4517 /* It MUST use the current LUT size to get the RSS lookup table,
4518 * otherwise if will fail with -100 error code.
4519 */
4520 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
4521 if (!lut) {
4522 PMD_DRV_LOG(ERR, "No memory can be allocated");
4523 return -ENOMEM;
4524 }
4525 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4526 if (ret)
4527 goto out;
4528
4529 for (i = 0; i < reta_size; i++) {
4530 idx = i / RTE_ETH_RETA_GROUP_SIZE;
4531 shift = i % RTE_ETH_RETA_GROUP_SIZE;
4532 if (reta_conf[idx].mask & (1ULL << shift))
4533 lut[i] = reta_conf[idx].reta[shift];
4534 }
4535 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4536 if (ret == 0 && lut_size != reta_size) {
4537 PMD_DRV_LOG(INFO,
4538 "The size of hash lookup table is changed from (%d) to (%d)",
4539 lut_size, reta_size);
4540 pf->hash_lut_size = reta_size;
4541 }
4542
4543 out:
4544 rte_free(lut);
4545
4546 return ret;
4547 }
4548
4549 static int
ice_rss_reta_query(struct rte_eth_dev * dev,struct rte_eth_rss_reta_entry64 * reta_conf,uint16_t reta_size)4550 ice_rss_reta_query(struct rte_eth_dev *dev,
4551 struct rte_eth_rss_reta_entry64 *reta_conf,
4552 uint16_t reta_size)
4553 {
4554 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4555 uint16_t i, lut_size = pf->hash_lut_size;
4556 uint16_t idx, shift;
4557 uint8_t *lut;
4558 int ret;
4559
4560 if (reta_size != lut_size) {
4561 PMD_DRV_LOG(ERR,
4562 "The size of hash lookup table configured (%d)"
4563 "doesn't match the number hardware can "
4564 "supported (%d)",
4565 reta_size, lut_size);
4566 return -EINVAL;
4567 }
4568
4569 lut = rte_zmalloc(NULL, reta_size, 0);
4570 if (!lut) {
4571 PMD_DRV_LOG(ERR, "No memory can be allocated");
4572 return -ENOMEM;
4573 }
4574
4575 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4576 if (ret)
4577 goto out;
4578
4579 for (i = 0; i < reta_size; i++) {
4580 idx = i / RTE_ETH_RETA_GROUP_SIZE;
4581 shift = i % RTE_ETH_RETA_GROUP_SIZE;
4582 if (reta_conf[idx].mask & (1ULL << shift))
4583 reta_conf[idx].reta[shift] = lut[i];
4584 }
4585
4586 out:
4587 rte_free(lut);
4588
4589 return ret;
4590 }
4591
4592 static int
ice_set_rss_key(struct ice_vsi * vsi,uint8_t * key,uint8_t key_len)4593 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4594 {
4595 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4596 int ret = 0;
4597
4598 if (!key || key_len == 0) {
4599 PMD_DRV_LOG(DEBUG, "No key to be configured");
4600 return 0;
4601 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4602 sizeof(uint32_t)) {
4603 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4604 return -EINVAL;
4605 }
4606
4607 struct ice_aqc_get_set_rss_keys *key_dw =
4608 (struct ice_aqc_get_set_rss_keys *)key;
4609
4610 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4611 if (ret) {
4612 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4613 ret = -EINVAL;
4614 }
4615
4616 return ret;
4617 }
4618
4619 static int
ice_get_rss_key(struct ice_vsi * vsi,uint8_t * key,uint8_t * key_len)4620 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4621 {
4622 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4623 int ret;
4624
4625 if (!key || !key_len)
4626 return -EINVAL;
4627
4628 ret = ice_aq_get_rss_key
4629 (hw, vsi->idx,
4630 (struct ice_aqc_get_set_rss_keys *)key);
4631 if (ret) {
4632 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4633 return -EINVAL;
4634 }
4635 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4636
4637 return 0;
4638 }
4639
4640 static int
ice_rss_hash_update(struct rte_eth_dev * dev,struct rte_eth_rss_conf * rss_conf)4641 ice_rss_hash_update(struct rte_eth_dev *dev,
4642 struct rte_eth_rss_conf *rss_conf)
4643 {
4644 enum ice_status status = ICE_SUCCESS;
4645 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4646 struct ice_vsi *vsi = pf->main_vsi;
4647
4648 /* set hash key */
4649 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4650 if (status)
4651 return status;
4652
4653 if (rss_conf->rss_hf == 0) {
4654 pf->rss_hf = 0;
4655 return 0;
4656 }
4657
4658 /* RSS hash configuration */
4659 ice_rss_hash_set(pf, rss_conf->rss_hf);
4660
4661 return 0;
4662 }
4663
4664 static int
ice_rss_hash_conf_get(struct rte_eth_dev * dev,struct rte_eth_rss_conf * rss_conf)4665 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4666 struct rte_eth_rss_conf *rss_conf)
4667 {
4668 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4669 struct ice_vsi *vsi = pf->main_vsi;
4670
4671 ice_get_rss_key(vsi, rss_conf->rss_key,
4672 &rss_conf->rss_key_len);
4673
4674 rss_conf->rss_hf = pf->rss_hf;
4675 return 0;
4676 }
4677
4678 static int
ice_promisc_enable(struct rte_eth_dev * dev)4679 ice_promisc_enable(struct rte_eth_dev *dev)
4680 {
4681 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4682 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4683 struct ice_vsi *vsi = pf->main_vsi;
4684 enum ice_status status;
4685 uint8_t pmask;
4686 int ret = 0;
4687
4688 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4689 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4690
4691 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4692 switch (status) {
4693 case ICE_ERR_ALREADY_EXISTS:
4694 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4695 case ICE_SUCCESS:
4696 break;
4697 default:
4698 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4699 ret = -EAGAIN;
4700 }
4701
4702 return ret;
4703 }
4704
4705 static int
ice_promisc_disable(struct rte_eth_dev * dev)4706 ice_promisc_disable(struct rte_eth_dev *dev)
4707 {
4708 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4709 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4710 struct ice_vsi *vsi = pf->main_vsi;
4711 enum ice_status status;
4712 uint8_t pmask;
4713 int ret = 0;
4714
4715 if (dev->data->all_multicast == 1)
4716 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4717 else
4718 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4719 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4720
4721 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4722 if (status != ICE_SUCCESS) {
4723 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4724 ret = -EAGAIN;
4725 }
4726
4727 return ret;
4728 }
4729
4730 static int
ice_allmulti_enable(struct rte_eth_dev * dev)4731 ice_allmulti_enable(struct rte_eth_dev *dev)
4732 {
4733 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4734 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735 struct ice_vsi *vsi = pf->main_vsi;
4736 enum ice_status status;
4737 uint8_t pmask;
4738 int ret = 0;
4739
4740 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4741
4742 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4743
4744 switch (status) {
4745 case ICE_ERR_ALREADY_EXISTS:
4746 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4747 case ICE_SUCCESS:
4748 break;
4749 default:
4750 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4751 ret = -EAGAIN;
4752 }
4753
4754 return ret;
4755 }
4756
4757 static int
ice_allmulti_disable(struct rte_eth_dev * dev)4758 ice_allmulti_disable(struct rte_eth_dev *dev)
4759 {
4760 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4761 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762 struct ice_vsi *vsi = pf->main_vsi;
4763 enum ice_status status;
4764 uint8_t pmask;
4765 int ret = 0;
4766
4767 if (dev->data->promiscuous == 1)
4768 return 0; /* must remain in all_multicast mode */
4769
4770 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4771
4772 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4773 if (status != ICE_SUCCESS) {
4774 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4775 ret = -EAGAIN;
4776 }
4777
4778 return ret;
4779 }
4780
ice_rx_queue_intr_enable(struct rte_eth_dev * dev,uint16_t queue_id)4781 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4782 uint16_t queue_id)
4783 {
4784 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4785 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
4786 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4787 uint32_t val;
4788 uint16_t msix_intr;
4789
4790 msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
4791
4792 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4793 GLINT_DYN_CTL_ITR_INDX_M;
4794 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4795
4796 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4797 rte_intr_ack(pci_dev->intr_handle);
4798
4799 return 0;
4800 }
4801
ice_rx_queue_intr_disable(struct rte_eth_dev * dev,uint16_t queue_id)4802 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4803 uint16_t queue_id)
4804 {
4805 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4806 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
4807 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4808 uint16_t msix_intr;
4809
4810 msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
4811
4812 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4813
4814 return 0;
4815 }
4816
4817 static int
ice_fw_version_get(struct rte_eth_dev * dev,char * fw_version,size_t fw_size)4818 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4819 {
4820 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4821 u8 ver, patch;
4822 u16 build;
4823 int ret;
4824
4825 ver = hw->flash.orom.major;
4826 patch = hw->flash.orom.patch;
4827 build = hw->flash.orom.build;
4828
4829 ret = snprintf(fw_version, fw_size,
4830 "%x.%02x 0x%08x %d.%d.%d",
4831 hw->flash.nvm.major,
4832 hw->flash.nvm.minor,
4833 hw->flash.nvm.eetrack,
4834 ver, build, patch);
4835 if (ret < 0)
4836 return -EINVAL;
4837
4838 /* add the size of '\0' */
4839 ret += 1;
4840 if (fw_size < (size_t)ret)
4841 return ret;
4842 else
4843 return 0;
4844 }
4845
4846 static int
ice_vsi_vlan_pvid_set(struct ice_vsi * vsi,struct ice_vsi_vlan_pvid_info * info)4847 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4848 {
4849 struct ice_hw *hw;
4850 struct ice_vsi_ctx ctxt;
4851 uint8_t vlan_flags = 0;
4852 int ret;
4853
4854 if (!vsi || !info) {
4855 PMD_DRV_LOG(ERR, "invalid parameters");
4856 return -EINVAL;
4857 }
4858
4859 if (info->on) {
4860 vsi->info.port_based_inner_vlan = info->config.pvid;
4861 /**
4862 * If insert pvid is enabled, only tagged pkts are
4863 * allowed to be sent out.
4864 */
4865 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4866 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4867 } else {
4868 vsi->info.port_based_inner_vlan = 0;
4869 if (info->config.reject.tagged == 0)
4870 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4871
4872 if (info->config.reject.untagged == 0)
4873 vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4874 }
4875 vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4876 ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4877 vsi->info.inner_vlan_flags |= vlan_flags;
4878 memset(&ctxt, 0, sizeof(ctxt));
4879 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4880 ctxt.info.valid_sections =
4881 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4882 ctxt.vsi_num = vsi->vsi_id;
4883
4884 hw = ICE_VSI_TO_HW(vsi);
4885 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4886 if (ret != ICE_SUCCESS) {
4887 PMD_DRV_LOG(ERR,
4888 "update VSI for VLAN insert failed, err %d",
4889 ret);
4890 return -EINVAL;
4891 }
4892
4893 vsi->info.valid_sections |=
4894 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4895
4896 return ret;
4897 }
4898
4899 static int
ice_vlan_pvid_set(struct rte_eth_dev * dev,uint16_t pvid,int on)4900 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4901 {
4902 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4903 struct ice_vsi *vsi = pf->main_vsi;
4904 struct rte_eth_dev_data *data = pf->dev_data;
4905 struct ice_vsi_vlan_pvid_info info;
4906 int ret;
4907
4908 memset(&info, 0, sizeof(info));
4909 info.on = on;
4910 if (info.on) {
4911 info.config.pvid = pvid;
4912 } else {
4913 info.config.reject.tagged =
4914 data->dev_conf.txmode.hw_vlan_reject_tagged;
4915 info.config.reject.untagged =
4916 data->dev_conf.txmode.hw_vlan_reject_untagged;
4917 }
4918
4919 ret = ice_vsi_vlan_pvid_set(vsi, &info);
4920 if (ret < 0) {
4921 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4922 return -EINVAL;
4923 }
4924
4925 return 0;
4926 }
4927
4928 static int
ice_get_eeprom_length(struct rte_eth_dev * dev)4929 ice_get_eeprom_length(struct rte_eth_dev *dev)
4930 {
4931 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4932
4933 return hw->flash.flash_size;
4934 }
4935
4936 static int
ice_get_eeprom(struct rte_eth_dev * dev,struct rte_dev_eeprom_info * eeprom)4937 ice_get_eeprom(struct rte_eth_dev *dev,
4938 struct rte_dev_eeprom_info *eeprom)
4939 {
4940 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941 enum ice_status status = ICE_SUCCESS;
4942 uint8_t *data = eeprom->data;
4943
4944 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4945
4946 status = ice_acquire_nvm(hw, ICE_RES_READ);
4947 if (status) {
4948 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4949 return -EIO;
4950 }
4951
4952 status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4953 data, false);
4954
4955 ice_release_nvm(hw);
4956
4957 if (status) {
4958 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4959 return -EIO;
4960 }
4961
4962 return 0;
4963 }
4964
4965 static int
ice_get_module_info(struct rte_eth_dev * dev,struct rte_eth_dev_module_info * modinfo)4966 ice_get_module_info(struct rte_eth_dev *dev,
4967 struct rte_eth_dev_module_info *modinfo)
4968 {
4969 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4970 enum ice_status status;
4971 u8 sff8472_comp = 0;
4972 u8 sff8472_swap = 0;
4973 u8 sff8636_rev = 0;
4974 u8 value = 0;
4975
4976 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR, 0x00, 0x00,
4977 0, &value, 1, 0, NULL);
4978 if (status)
4979 return -EIO;
4980
4981 switch (value) {
4982 case ICE_MODULE_TYPE_SFP:
4983 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR,
4984 ICE_MODULE_SFF_8472_COMP, 0x00, 0,
4985 &sff8472_comp, 1, 0, NULL);
4986 if (status)
4987 return -EIO;
4988 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR,
4989 ICE_MODULE_SFF_8472_SWAP, 0x00, 0,
4990 &sff8472_swap, 1, 0, NULL);
4991 if (status)
4992 return -EIO;
4993
4994 if (sff8472_swap & ICE_MODULE_SFF_ADDR_MODE) {
4995 modinfo->type = ICE_MODULE_SFF_8079;
4996 modinfo->eeprom_len = ICE_MODULE_SFF_8079_LEN;
4997 } else if (sff8472_comp &&
4998 (sff8472_swap & ICE_MODULE_SFF_DIAG_CAPAB)) {
4999 modinfo->type = ICE_MODULE_SFF_8472;
5000 modinfo->eeprom_len = ICE_MODULE_SFF_8472_LEN;
5001 } else {
5002 modinfo->type = ICE_MODULE_SFF_8079;
5003 modinfo->eeprom_len = ICE_MODULE_SFF_8079_LEN;
5004 }
5005 break;
5006 case ICE_MODULE_TYPE_QSFP_PLUS:
5007 case ICE_MODULE_TYPE_QSFP28:
5008 status = ice_aq_sff_eeprom(hw, 0, ICE_I2C_EEPROM_DEV_ADDR,
5009 ICE_MODULE_REVISION_ADDR, 0x00, 0,
5010 &sff8636_rev, 1, 0, NULL);
5011 if (status)
5012 return -EIO;
5013 /* Check revision compliance */
5014 if (sff8636_rev > 0x02) {
5015 /* Module is SFF-8636 compliant */
5016 modinfo->type = ICE_MODULE_SFF_8636;
5017 modinfo->eeprom_len = ICE_MODULE_QSFP_MAX_LEN;
5018 } else {
5019 modinfo->type = ICE_MODULE_SFF_8436;
5020 modinfo->eeprom_len = ICE_MODULE_QSFP_MAX_LEN;
5021 }
5022 break;
5023 default:
5024 PMD_DRV_LOG(WARNING, "SFF Module Type not recognized.\n");
5025 return -EINVAL;
5026 }
5027 return 0;
5028 }
5029
5030 static int
ice_get_module_eeprom(struct rte_eth_dev * dev,struct rte_dev_eeprom_info * info)5031 ice_get_module_eeprom(struct rte_eth_dev *dev,
5032 struct rte_dev_eeprom_info *info)
5033 {
5034 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035 #define SFF_READ_BLOCK_SIZE 8
5036 #define I2C_BUSY_TRY_TIMES 4
5037 #define I2C_USLEEP_MIN_TIME 1500
5038 #define I2C_USLEEP_MAX_TIME 2500
5039 uint8_t value[SFF_READ_BLOCK_SIZE] = {0};
5040 uint8_t addr = ICE_I2C_EEPROM_DEV_ADDR;
5041 uint8_t *data = NULL;
5042 enum ice_status status;
5043 bool is_sfp = false;
5044 uint32_t i, j;
5045 uint32_t offset = 0;
5046 uint8_t page = 0;
5047
5048 if (!info || !info->length || !info->data)
5049 return -EINVAL;
5050
5051 status = ice_aq_sff_eeprom(hw, 0, addr, offset, page, 0, value, 1, 0,
5052 NULL);
5053 if (status)
5054 return -EIO;
5055
5056 if (value[0] == ICE_MODULE_TYPE_SFP)
5057 is_sfp = true;
5058
5059 data = info->data;
5060 memset(data, 0, info->length);
5061 for (i = 0; i < info->length; i += SFF_READ_BLOCK_SIZE) {
5062 offset = i + info->offset;
5063 page = 0;
5064
5065 /* Check if we need to access the other memory page */
5066 if (is_sfp) {
5067 if (offset >= ICE_MODULE_SFF_8079_LEN) {
5068 offset -= ICE_MODULE_SFF_8079_LEN;
5069 addr = ICE_I2C_EEPROM_DEV_ADDR2;
5070 }
5071 } else {
5072 while (offset >= ICE_MODULE_SFF_8436_LEN) {
5073 /* Compute memory page number and offset. */
5074 offset -= ICE_MODULE_SFF_8436_LEN / 2;
5075 page++;
5076 }
5077 }
5078
5079 /* Bit 2 of eeprom address 0x02 declares upper
5080 * pages are disabled on QSFP modules.
5081 * SFP modules only ever use page 0.
5082 */
5083 if (page == 0 || !(data[0x2] & 0x4)) {
5084 /* If i2c bus is busy due to slow page change or
5085 * link management access, call can fail.
5086 * This is normal. So we retry this a few times.
5087 */
5088 for (j = 0; j < I2C_BUSY_TRY_TIMES; j++) {
5089 status = ice_aq_sff_eeprom(hw, 0, addr, offset,
5090 page, !is_sfp, value,
5091 SFF_READ_BLOCK_SIZE,
5092 0, NULL);
5093 PMD_DRV_LOG(DEBUG, "SFF %02X %02X %02X %X = "
5094 "%02X%02X%02X%02X."
5095 "%02X%02X%02X%02X (%X)\n",
5096 addr, offset, page, is_sfp,
5097 value[0], value[1],
5098 value[2], value[3],
5099 value[4], value[5],
5100 value[6], value[7],
5101 status);
5102 if (status) {
5103 usleep_range(I2C_USLEEP_MIN_TIME,
5104 I2C_USLEEP_MAX_TIME);
5105 memset(value, 0, SFF_READ_BLOCK_SIZE);
5106 continue;
5107 }
5108 break;
5109 }
5110
5111 /* Make sure we have enough room for the new block */
5112 if ((i + SFF_READ_BLOCK_SIZE) < info->length)
5113 memcpy(data + i, value, SFF_READ_BLOCK_SIZE);
5114 }
5115 }
5116
5117 return 0;
5118 }
5119
5120 static void
ice_stat_update_32(struct ice_hw * hw,uint32_t reg,bool offset_loaded,uint64_t * offset,uint64_t * stat)5121 ice_stat_update_32(struct ice_hw *hw,
5122 uint32_t reg,
5123 bool offset_loaded,
5124 uint64_t *offset,
5125 uint64_t *stat)
5126 {
5127 uint64_t new_data;
5128
5129 new_data = (uint64_t)ICE_READ_REG(hw, reg);
5130 if (!offset_loaded)
5131 *offset = new_data;
5132
5133 if (new_data >= *offset)
5134 *stat = (uint64_t)(new_data - *offset);
5135 else
5136 *stat = (uint64_t)((new_data +
5137 ((uint64_t)1 << ICE_32_BIT_WIDTH))
5138 - *offset);
5139 }
5140
5141 static void
ice_stat_update_40(struct ice_hw * hw,uint32_t hireg,uint32_t loreg,bool offset_loaded,uint64_t * offset,uint64_t * stat)5142 ice_stat_update_40(struct ice_hw *hw,
5143 uint32_t hireg,
5144 uint32_t loreg,
5145 bool offset_loaded,
5146 uint64_t *offset,
5147 uint64_t *stat)
5148 {
5149 uint64_t new_data;
5150
5151 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
5152 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
5153 ICE_32_BIT_WIDTH;
5154
5155 if (!offset_loaded)
5156 *offset = new_data;
5157
5158 if (new_data >= *offset)
5159 *stat = new_data - *offset;
5160 else
5161 *stat = (uint64_t)((new_data +
5162 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
5163 *offset);
5164
5165 *stat &= ICE_40_BIT_MASK;
5166 }
5167
5168 /* Get all the statistics of a VSI */
5169 static void
ice_update_vsi_stats(struct ice_vsi * vsi)5170 ice_update_vsi_stats(struct ice_vsi *vsi)
5171 {
5172 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
5173 struct ice_eth_stats *nes = &vsi->eth_stats;
5174 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
5175 int idx = rte_le_to_cpu_16(vsi->vsi_id);
5176
5177 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
5178 vsi->offset_loaded, &oes->rx_bytes,
5179 &nes->rx_bytes);
5180 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
5181 vsi->offset_loaded, &oes->rx_unicast,
5182 &nes->rx_unicast);
5183 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
5184 vsi->offset_loaded, &oes->rx_multicast,
5185 &nes->rx_multicast);
5186 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
5187 vsi->offset_loaded, &oes->rx_broadcast,
5188 &nes->rx_broadcast);
5189 /* enlarge the limitation when rx_bytes overflowed */
5190 if (vsi->offset_loaded) {
5191 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
5192 nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5193 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
5194 }
5195 vsi->old_rx_bytes = nes->rx_bytes;
5196 /* exclude CRC bytes */
5197 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
5198 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
5199
5200 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
5201 &oes->rx_discards, &nes->rx_discards);
5202 /* GLV_REPC not supported */
5203 /* GLV_RMPC not supported */
5204 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
5205 &oes->rx_unknown_protocol,
5206 &nes->rx_unknown_protocol);
5207 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
5208 vsi->offset_loaded, &oes->tx_bytes,
5209 &nes->tx_bytes);
5210 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
5211 vsi->offset_loaded, &oes->tx_unicast,
5212 &nes->tx_unicast);
5213 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
5214 vsi->offset_loaded, &oes->tx_multicast,
5215 &nes->tx_multicast);
5216 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
5217 vsi->offset_loaded, &oes->tx_broadcast,
5218 &nes->tx_broadcast);
5219 /* GLV_TDPC not supported */
5220 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
5221 &oes->tx_errors, &nes->tx_errors);
5222 /* enlarge the limitation when tx_bytes overflowed */
5223 if (vsi->offset_loaded) {
5224 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
5225 nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5226 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
5227 }
5228 vsi->old_tx_bytes = nes->tx_bytes;
5229 vsi->offset_loaded = true;
5230
5231 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
5232 vsi->vsi_id);
5233 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
5234 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
5235 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
5236 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
5237 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
5238 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5239 nes->rx_unknown_protocol);
5240 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
5241 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
5242 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
5243 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
5244 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
5245 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
5246 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
5247 vsi->vsi_id);
5248 }
5249
5250 static void
ice_read_stats_registers(struct ice_pf * pf,struct ice_hw * hw)5251 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
5252 {
5253 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5254 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
5255
5256 /* Get statistics of struct ice_eth_stats */
5257 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
5258 GLPRT_GORCL(hw->port_info->lport),
5259 pf->offset_loaded, &os->eth.rx_bytes,
5260 &ns->eth.rx_bytes);
5261 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
5262 GLPRT_UPRCL(hw->port_info->lport),
5263 pf->offset_loaded, &os->eth.rx_unicast,
5264 &ns->eth.rx_unicast);
5265 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
5266 GLPRT_MPRCL(hw->port_info->lport),
5267 pf->offset_loaded, &os->eth.rx_multicast,
5268 &ns->eth.rx_multicast);
5269 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
5270 GLPRT_BPRCL(hw->port_info->lport),
5271 pf->offset_loaded, &os->eth.rx_broadcast,
5272 &ns->eth.rx_broadcast);
5273 ice_stat_update_32(hw, PRTRPB_RDPC,
5274 pf->offset_loaded, &os->eth.rx_discards,
5275 &ns->eth.rx_discards);
5276 /* enlarge the limitation when rx_bytes overflowed */
5277 if (pf->offset_loaded) {
5278 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
5279 ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5280 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
5281 }
5282 pf->old_rx_bytes = ns->eth.rx_bytes;
5283
5284 /* Workaround: CRC size should not be included in byte statistics,
5285 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
5286 * packet.
5287 */
5288 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
5289 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
5290
5291 /* GLPRT_REPC not supported */
5292 /* GLPRT_RMPC not supported */
5293 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
5294 pf->offset_loaded,
5295 &os->eth.rx_unknown_protocol,
5296 &ns->eth.rx_unknown_protocol);
5297 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
5298 GLPRT_GOTCL(hw->port_info->lport),
5299 pf->offset_loaded, &os->eth.tx_bytes,
5300 &ns->eth.tx_bytes);
5301 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
5302 GLPRT_UPTCL(hw->port_info->lport),
5303 pf->offset_loaded, &os->eth.tx_unicast,
5304 &ns->eth.tx_unicast);
5305 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
5306 GLPRT_MPTCL(hw->port_info->lport),
5307 pf->offset_loaded, &os->eth.tx_multicast,
5308 &ns->eth.tx_multicast);
5309 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
5310 GLPRT_BPTCL(hw->port_info->lport),
5311 pf->offset_loaded, &os->eth.tx_broadcast,
5312 &ns->eth.tx_broadcast);
5313 /* enlarge the limitation when tx_bytes overflowed */
5314 if (pf->offset_loaded) {
5315 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
5316 ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
5317 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
5318 }
5319 pf->old_tx_bytes = ns->eth.tx_bytes;
5320 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
5321 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
5322
5323 /* GLPRT_TEPC not supported */
5324
5325 /* additional port specific stats */
5326 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
5327 pf->offset_loaded, &os->tx_dropped_link_down,
5328 &ns->tx_dropped_link_down);
5329 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
5330 pf->offset_loaded, &os->crc_errors,
5331 &ns->crc_errors);
5332 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
5333 pf->offset_loaded, &os->illegal_bytes,
5334 &ns->illegal_bytes);
5335 /* GLPRT_ERRBC not supported */
5336 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
5337 pf->offset_loaded, &os->mac_local_faults,
5338 &ns->mac_local_faults);
5339 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
5340 pf->offset_loaded, &os->mac_remote_faults,
5341 &ns->mac_remote_faults);
5342
5343 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
5344 pf->offset_loaded, &os->rx_len_errors,
5345 &ns->rx_len_errors);
5346
5347 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
5348 pf->offset_loaded, &os->link_xon_rx,
5349 &ns->link_xon_rx);
5350 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
5351 pf->offset_loaded, &os->link_xoff_rx,
5352 &ns->link_xoff_rx);
5353 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
5354 pf->offset_loaded, &os->link_xon_tx,
5355 &ns->link_xon_tx);
5356 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
5357 pf->offset_loaded, &os->link_xoff_tx,
5358 &ns->link_xoff_tx);
5359 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
5360 GLPRT_PRC64L(hw->port_info->lport),
5361 pf->offset_loaded, &os->rx_size_64,
5362 &ns->rx_size_64);
5363 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
5364 GLPRT_PRC127L(hw->port_info->lport),
5365 pf->offset_loaded, &os->rx_size_127,
5366 &ns->rx_size_127);
5367 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5368 GLPRT_PRC255L(hw->port_info->lport),
5369 pf->offset_loaded, &os->rx_size_255,
5370 &ns->rx_size_255);
5371 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5372 GLPRT_PRC511L(hw->port_info->lport),
5373 pf->offset_loaded, &os->rx_size_511,
5374 &ns->rx_size_511);
5375 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5376 GLPRT_PRC1023L(hw->port_info->lport),
5377 pf->offset_loaded, &os->rx_size_1023,
5378 &ns->rx_size_1023);
5379 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5380 GLPRT_PRC1522L(hw->port_info->lport),
5381 pf->offset_loaded, &os->rx_size_1522,
5382 &ns->rx_size_1522);
5383 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5384 GLPRT_PRC9522L(hw->port_info->lport),
5385 pf->offset_loaded, &os->rx_size_big,
5386 &ns->rx_size_big);
5387 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5388 pf->offset_loaded, &os->rx_undersize,
5389 &ns->rx_undersize);
5390 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5391 pf->offset_loaded, &os->rx_fragments,
5392 &ns->rx_fragments);
5393 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5394 pf->offset_loaded, &os->rx_oversize,
5395 &ns->rx_oversize);
5396 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5397 pf->offset_loaded, &os->rx_jabber,
5398 &ns->rx_jabber);
5399 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5400 GLPRT_PTC64L(hw->port_info->lport),
5401 pf->offset_loaded, &os->tx_size_64,
5402 &ns->tx_size_64);
5403 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5404 GLPRT_PTC127L(hw->port_info->lport),
5405 pf->offset_loaded, &os->tx_size_127,
5406 &ns->tx_size_127);
5407 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5408 GLPRT_PTC255L(hw->port_info->lport),
5409 pf->offset_loaded, &os->tx_size_255,
5410 &ns->tx_size_255);
5411 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5412 GLPRT_PTC511L(hw->port_info->lport),
5413 pf->offset_loaded, &os->tx_size_511,
5414 &ns->tx_size_511);
5415 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5416 GLPRT_PTC1023L(hw->port_info->lport),
5417 pf->offset_loaded, &os->tx_size_1023,
5418 &ns->tx_size_1023);
5419 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5420 GLPRT_PTC1522L(hw->port_info->lport),
5421 pf->offset_loaded, &os->tx_size_1522,
5422 &ns->tx_size_1522);
5423 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5424 GLPRT_PTC9522L(hw->port_info->lport),
5425 pf->offset_loaded, &os->tx_size_big,
5426 &ns->tx_size_big);
5427
5428 /* GLPRT_MSPDC not supported */
5429 /* GLPRT_XEC not supported */
5430
5431 pf->offset_loaded = true;
5432
5433 if (pf->main_vsi)
5434 ice_update_vsi_stats(pf->main_vsi);
5435 }
5436
5437 /* Get all statistics of a port */
5438 static int
ice_stats_get(struct rte_eth_dev * dev,struct rte_eth_stats * stats)5439 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5440 {
5441 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5442 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5443 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5444
5445 /* call read registers - updates values, now write them to struct */
5446 ice_read_stats_registers(pf, hw);
5447
5448 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5449 pf->main_vsi->eth_stats.rx_multicast +
5450 pf->main_vsi->eth_stats.rx_broadcast -
5451 pf->main_vsi->eth_stats.rx_discards;
5452 stats->opackets = ns->eth.tx_unicast +
5453 ns->eth.tx_multicast +
5454 ns->eth.tx_broadcast;
5455 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
5456 stats->obytes = ns->eth.tx_bytes;
5457 stats->oerrors = ns->eth.tx_errors +
5458 pf->main_vsi->eth_stats.tx_errors;
5459
5460 /* Rx Errors */
5461 stats->imissed = ns->eth.rx_discards +
5462 pf->main_vsi->eth_stats.rx_discards;
5463 stats->ierrors = ns->crc_errors +
5464 ns->rx_undersize +
5465 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5466
5467 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5468 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
5469 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5470 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5471 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5472 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5473 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5474 pf->main_vsi->eth_stats.rx_discards);
5475 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
5476 ns->eth.rx_unknown_protocol);
5477 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
5478 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5479 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5480 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5481 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5482 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5483 pf->main_vsi->eth_stats.tx_discards);
5484 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
5485
5486 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
5487 ns->tx_dropped_link_down);
5488 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5489 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
5490 ns->illegal_bytes);
5491 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
5492 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
5493 ns->mac_local_faults);
5494 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
5495 ns->mac_remote_faults);
5496 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
5497 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
5498 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
5499 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
5500 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
5501 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
5502 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
5503 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
5504 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
5505 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
5506 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
5507 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
5508 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
5509 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
5510 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
5511 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
5512 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
5513 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
5514 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
5515 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
5516 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
5517 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
5518 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
5519 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5520 return 0;
5521 }
5522
5523 /* Reset the statistics */
5524 static int
ice_stats_reset(struct rte_eth_dev * dev)5525 ice_stats_reset(struct rte_eth_dev *dev)
5526 {
5527 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5528 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529
5530 /* Mark PF and VSI stats to update the offset, aka "reset" */
5531 pf->offset_loaded = false;
5532 if (pf->main_vsi)
5533 pf->main_vsi->offset_loaded = false;
5534
5535 /* read the stats, reading current register values into offset */
5536 ice_read_stats_registers(pf, hw);
5537
5538 return 0;
5539 }
5540
5541 static uint32_t
ice_xstats_calc_num(void)5542 ice_xstats_calc_num(void)
5543 {
5544 uint32_t num;
5545
5546 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5547
5548 return num;
5549 }
5550
5551 static int
ice_xstats_get(struct rte_eth_dev * dev,struct rte_eth_xstat * xstats,unsigned int n)5552 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5553 unsigned int n)
5554 {
5555 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5556 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5557 unsigned int i;
5558 unsigned int count;
5559 struct ice_hw_port_stats *hw_stats = &pf->stats;
5560
5561 count = ice_xstats_calc_num();
5562 if (n < count)
5563 return count;
5564
5565 ice_read_stats_registers(pf, hw);
5566
5567 if (!xstats)
5568 return 0;
5569
5570 count = 0;
5571
5572 /* Get stats from ice_eth_stats struct */
5573 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5574 xstats[count].value =
5575 *(uint64_t *)((char *)&hw_stats->eth +
5576 ice_stats_strings[i].offset);
5577 xstats[count].id = count;
5578 count++;
5579 }
5580
5581 /* Get individual stats from ice_hw_port struct */
5582 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5583 xstats[count].value =
5584 *(uint64_t *)((char *)hw_stats +
5585 ice_hw_port_strings[i].offset);
5586 xstats[count].id = count;
5587 count++;
5588 }
5589
5590 return count;
5591 }
5592
ice_xstats_get_names(__rte_unused struct rte_eth_dev * dev,struct rte_eth_xstat_name * xstats_names,__rte_unused unsigned int limit)5593 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5594 struct rte_eth_xstat_name *xstats_names,
5595 __rte_unused unsigned int limit)
5596 {
5597 unsigned int count = 0;
5598 unsigned int i;
5599
5600 if (!xstats_names)
5601 return ice_xstats_calc_num();
5602
5603 /* Note: limit checked in rte_eth_xstats_names() */
5604
5605 /* Get stats from ice_eth_stats struct */
5606 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5607 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5608 sizeof(xstats_names[count].name));
5609 count++;
5610 }
5611
5612 /* Get individual stats from ice_hw_port struct */
5613 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5614 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5615 sizeof(xstats_names[count].name));
5616 count++;
5617 }
5618
5619 return count;
5620 }
5621
5622 static int
ice_dev_flow_ops_get(struct rte_eth_dev * dev,const struct rte_flow_ops ** ops)5623 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5624 const struct rte_flow_ops **ops)
5625 {
5626 if (!dev)
5627 return -EINVAL;
5628
5629 *ops = &ice_flow_ops;
5630 return 0;
5631 }
5632
5633 /* Add UDP tunneling port */
5634 static int
ice_dev_udp_tunnel_port_add(struct rte_eth_dev * dev,struct rte_eth_udp_tunnel * udp_tunnel)5635 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5636 struct rte_eth_udp_tunnel *udp_tunnel)
5637 {
5638 int ret = 0;
5639 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5640 struct ice_adapter *ad =
5641 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5642
5643 if (udp_tunnel == NULL)
5644 return -EINVAL;
5645
5646 switch (udp_tunnel->prot_type) {
5647 case RTE_ETH_TUNNEL_TYPE_VXLAN:
5648 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5649 if (!ret && ad->psr != NULL)
5650 ice_parser_vxlan_tunnel_set(ad->psr,
5651 udp_tunnel->udp_port, true);
5652 break;
5653 default:
5654 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5655 ret = -EINVAL;
5656 break;
5657 }
5658
5659 return ret;
5660 }
5661
5662 /* Delete UDP tunneling port */
5663 static int
ice_dev_udp_tunnel_port_del(struct rte_eth_dev * dev,struct rte_eth_udp_tunnel * udp_tunnel)5664 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5665 struct rte_eth_udp_tunnel *udp_tunnel)
5666 {
5667 int ret = 0;
5668 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5669 struct ice_adapter *ad =
5670 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5671
5672 if (udp_tunnel == NULL)
5673 return -EINVAL;
5674
5675 switch (udp_tunnel->prot_type) {
5676 case RTE_ETH_TUNNEL_TYPE_VXLAN:
5677 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5678 if (!ret && ad->psr != NULL)
5679 ice_parser_vxlan_tunnel_set(ad->psr,
5680 udp_tunnel->udp_port, false);
5681 break;
5682 default:
5683 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5684 ret = -EINVAL;
5685 break;
5686 }
5687
5688 return ret;
5689 }
5690
5691 static int
ice_timesync_enable(struct rte_eth_dev * dev)5692 ice_timesync_enable(struct rte_eth_dev *dev)
5693 {
5694 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695 struct ice_adapter *ad =
5696 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5697 int ret;
5698
5699 if (dev->data->dev_started && !(dev->data->dev_conf.rxmode.offloads &
5700 RTE_ETH_RX_OFFLOAD_TIMESTAMP)) {
5701 PMD_DRV_LOG(ERR, "Rx timestamp offload not configured");
5702 return -1;
5703 }
5704
5705 if (hw->func_caps.ts_func_info.src_tmr_owned) {
5706 ret = ice_ptp_init_phc(hw);
5707 if (ret) {
5708 PMD_DRV_LOG(ERR, "Failed to initialize PHC");
5709 return -1;
5710 }
5711
5712 ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810);
5713 if (ret) {
5714 PMD_DRV_LOG(ERR,
5715 "Failed to write PHC increment time value");
5716 return -1;
5717 }
5718 }
5719
5720 /* Initialize cycle counters for system time/RX/TX timestamp */
5721 memset(&ad->systime_tc, 0, sizeof(struct rte_timecounter));
5722 memset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5723 memset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5724
5725 ad->systime_tc.cc_mask = ICE_CYCLECOUNTER_MASK;
5726 ad->systime_tc.cc_shift = 0;
5727 ad->systime_tc.nsec_mask = 0;
5728
5729 ad->rx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;
5730 ad->rx_tstamp_tc.cc_shift = 0;
5731 ad->rx_tstamp_tc.nsec_mask = 0;
5732
5733 ad->tx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;
5734 ad->tx_tstamp_tc.cc_shift = 0;
5735 ad->tx_tstamp_tc.nsec_mask = 0;
5736
5737 ad->ptp_ena = 1;
5738
5739 return 0;
5740 }
5741
5742 static int
ice_timesync_read_rx_timestamp(struct rte_eth_dev * dev,struct timespec * timestamp,uint32_t flags)5743 ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5744 struct timespec *timestamp, uint32_t flags)
5745 {
5746 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5747 struct ice_adapter *ad =
5748 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5749 struct ice_rx_queue *rxq;
5750 uint32_t ts_high;
5751 uint64_t ts_ns, ns;
5752
5753 rxq = dev->data->rx_queues[flags];
5754
5755 ts_high = rxq->time_high;
5756 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, ts_high);
5757 ns = rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns);
5758 *timestamp = rte_ns_to_timespec(ns);
5759
5760 return 0;
5761 }
5762
5763 static int
ice_timesync_read_tx_timestamp(struct rte_eth_dev * dev,struct timespec * timestamp)5764 ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5765 struct timespec *timestamp)
5766 {
5767 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5768 struct ice_adapter *ad =
5769 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5770 uint8_t lport;
5771 uint64_t ts_ns, ns, tstamp;
5772 const uint64_t mask = 0xFFFFFFFF;
5773 int ret;
5774
5775 lport = hw->port_info->lport;
5776
5777 ret = ice_read_phy_tstamp(hw, lport, 0, &tstamp);
5778 if (ret) {
5779 PMD_DRV_LOG(ERR, "Failed to read phy timestamp");
5780 return -1;
5781 }
5782
5783 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, (tstamp >> 8) & mask);
5784 ns = rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns);
5785 *timestamp = rte_ns_to_timespec(ns);
5786
5787 return 0;
5788 }
5789
5790 static int
ice_timesync_adjust_time(struct rte_eth_dev * dev,int64_t delta)5791 ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5792 {
5793 struct ice_adapter *ad =
5794 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5795
5796 ad->systime_tc.nsec += delta;
5797 ad->rx_tstamp_tc.nsec += delta;
5798 ad->tx_tstamp_tc.nsec += delta;
5799
5800 return 0;
5801 }
5802
5803 static int
ice_timesync_write_time(struct rte_eth_dev * dev,const struct timespec * ts)5804 ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5805 {
5806 struct ice_adapter *ad =
5807 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5808 uint64_t ns;
5809
5810 ns = rte_timespec_to_ns(ts);
5811
5812 ad->systime_tc.nsec = ns;
5813 ad->rx_tstamp_tc.nsec = ns;
5814 ad->tx_tstamp_tc.nsec = ns;
5815
5816 return 0;
5817 }
5818
5819 static int
ice_timesync_read_time(struct rte_eth_dev * dev,struct timespec * ts)5820 ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5821 {
5822 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823 struct ice_adapter *ad =
5824 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5825 uint32_t hi, lo, lo2;
5826 uint64_t time, ns;
5827
5828 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
5829 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));
5830 lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
5831
5832 if (lo2 < lo) {
5833 lo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));
5834 hi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));
5835 }
5836
5837 time = ((uint64_t)hi << 32) | lo;
5838 ns = rte_timecounter_update(&ad->systime_tc, time);
5839 *ts = rte_ns_to_timespec(ns);
5840
5841 return 0;
5842 }
5843
5844 static int
ice_timesync_disable(struct rte_eth_dev * dev)5845 ice_timesync_disable(struct rte_eth_dev *dev)
5846 {
5847 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5848 struct ice_adapter *ad =
5849 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
5850 uint64_t val;
5851 uint8_t lport;
5852
5853 lport = hw->port_info->lport;
5854
5855 ice_clear_phy_tstamp(hw, lport, 0);
5856
5857 val = ICE_READ_REG(hw, GLTSYN_ENA(0));
5858 val &= ~GLTSYN_ENA_TSYN_ENA_M;
5859 ICE_WRITE_REG(hw, GLTSYN_ENA(0), val);
5860
5861 ICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0);
5862 ICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0);
5863
5864 ad->ptp_ena = 0;
5865
5866 return 0;
5867 }
5868
5869 static int
ice_pci_probe(struct rte_pci_driver * pci_drv __rte_unused,struct rte_pci_device * pci_dev)5870 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5871 struct rte_pci_device *pci_dev)
5872 {
5873 return rte_eth_dev_pci_generic_probe(pci_dev,
5874 sizeof(struct ice_adapter),
5875 ice_dev_init);
5876 }
5877
5878 static int
ice_pci_remove(struct rte_pci_device * pci_dev)5879 ice_pci_remove(struct rte_pci_device *pci_dev)
5880 {
5881 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5882 }
5883
5884 static struct rte_pci_driver rte_ice_pmd = {
5885 .id_table = pci_id_ice_map,
5886 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5887 .probe = ice_pci_probe,
5888 .remove = ice_pci_remove,
5889 };
5890
5891 /**
5892 * Driver initialization routine.
5893 * Invoked once at EAL init time.
5894 * Register itself as the [Poll Mode] Driver of PCI devices.
5895 */
5896 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5897 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5898 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5899 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5900 ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5901 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5902 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5903 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
5904 ICE_RX_LOW_LATENCY_ARG "=<0|1>");
5905
5906 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5907 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5908 #ifdef RTE_ETHDEV_DEBUG_RX
5909 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5910 #endif
5911 #ifdef RTE_ETHDEV_DEBUG_TX
5912 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);
5913 #endif
5914