Searched refs:default_rxportconf (Results 1 – 23 of 23) sorted by relevance
241 info->default_rxportconf.ring_size = 256; in mlx5_set_default_params()243 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; in mlx5_set_default_params()247 info->default_rxportconf.nb_queues = 16; in mlx5_set_default_params()252 info->default_rxportconf.ring_size = 2048; in mlx5_set_default_params()256 info->default_rxportconf.nb_queues = 8; in mlx5_set_default_params()261 info->default_rxportconf.ring_size = 4096; in mlx5_set_default_params()
134 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; in hns3_dev_infos_get()136 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; in hns3_dev_infos_get()138 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; in hns3_dev_infos_get()
438 dev_info->default_rxportconf.burst_size = 32; in ionic_dev_info_get()440 dev_info->default_rxportconf.nb_queues = 1; in ionic_dev_info_get()442 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; in ionic_dev_info_get()
364 info->default_rxportconf = vf_info.default_rxportconf; in hn_vf_info_merge()
799 dev_info->default_rxportconf.burst_size = ETH_AF_XDP_DFLT_BUSY_BUDGET; in eth_dev_info()801 dev_info->default_rxportconf.nb_queues = 1; in eth_dev_info()803 dev_info->default_rxportconf.ring_size = ETH_AF_XDP_DFLT_NUM_DESCS; in eth_dev_info()
587 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; in dpaa_eth_dev_info()589 dev_info->default_rxportconf.nb_queues = 1; in dpaa_eth_dev_info()592 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; in dpaa_eth_dev_info()
268 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; in dpaa2_dev_info_get()272 dev_info->default_rxportconf.nb_queues = 1; in dpaa2_dev_info_get()275 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; in dpaa2_dev_info_get()
1107 dev_info->default_rxportconf.nb_queues = 1; in eth_em_infos_get()1110 dev_info->default_rxportconf.ring_size = 256; in eth_em_infos_get()
763 info->default_rxportconf.burst_size = HINIC_DEFAULT_BURST_SIZE; in hinic_dev_infos_get()765 info->default_rxportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES; in hinic_dev_infos_get()767 info->default_rxportconf.ring_size = HINIC_DEFAULT_RING_SIZE; in hinic_dev_infos_get()
1800 dev_info->default_rxportconf.burst_size = 32; in ngbe_dev_info_get()1802 dev_info->default_rxportconf.nb_queues = 1; in ngbe_dev_info_get()1804 dev_info->default_rxportconf.ring_size = 256; in ngbe_dev_info_get()
45 devinfo->default_rxportconf = (struct rte_eth_dev_portconf){ in cnxk_nix_info_get()
3802 dev_info->default_rxportconf.nb_queues = 2; in i40e_dev_info_get()3805 dev_info->default_rxportconf.ring_size = 2048; in i40e_dev_info_get()3807 dev_info->default_rxportconf.ring_size = 1024; in i40e_dev_info_get()3816 dev_info->default_rxportconf.nb_queues = 1; in i40e_dev_info_get()3818 dev_info->default_rxportconf.ring_size = 256; in i40e_dev_info_get()3823 dev_info->default_rxportconf.nb_queues = 1; in i40e_dev_info_get()3826 dev_info->default_rxportconf.ring_size = 512; in i40e_dev_info_get()3829 dev_info->default_rxportconf.ring_size = 256; in i40e_dev_info_get()3833 dev_info->default_rxportconf.burst_size = 32; in i40e_dev_info_get()
1181 .default_rxportconf.burst_size; in launch_args_parse()
3373 else if (port->dev_info.default_rxportconf.ring_size) in get_rx_ring_size()3374 *ring_size = port->dev_info.default_rxportconf.ring_size; in get_rx_ring_size()
3401 rec_nb_pkts = dev_info.default_rxportconf.burst_size; in cmd_config_burst_parsed()
491 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { in enicpmd_dev_info_get()
2638 dev_info->default_rxportconf.burst_size = 32; in txgbe_dev_info_get()2640 dev_info->default_rxportconf.nb_queues = 1; in txgbe_dev_info_get()2642 dev_info->default_rxportconf.ring_size = 256; in txgbe_dev_info_get()
3806 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST; in ice_dev_info_get()3808 dev_info->default_rxportconf.nb_queues = 1; in ice_dev_info_get()3810 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN; in ice_dev_info_get()
1902 struct rte_eth_dev_portconf default_rxportconf; member
1129 nb_rx_q = dev_info.default_rxportconf.nb_queues; in rte_eth_dev_configure()1795 nb_rx_desc = dev_info.default_rxportconf.ring_size; in rte_eth_rx_queue_setup()
3923 dev_info->default_rxportconf.burst_size = 32; in ixgbe_dev_info_get()3925 dev_info->default_rxportconf.nb_queues = 1; in ixgbe_dev_info_get()3927 dev_info->default_rxportconf.ring_size = 256; in ixgbe_dev_info_get()
484 end of it: ``default_rxportconf`` and ``default_txportconf``. Each of these
2479 dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; in ena_infos_get()