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Searched defs:reg_addr (Results 1 – 25 of 30) sorted by relevance

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/dpdk/drivers/crypto/nitrox/
H A Dnitrox_hal.c22 uint64_t reg_addr; in nps_pkt_input_ring_disable() local
43 uint64_t reg_addr; in nps_pkt_solicited_port_disable() local
68 uint64_t base_addr, reg_addr; in setup_nps_pkt_input_ring() local
128 uint64_t reg_addr; in setup_nps_pkt_solicit_output_port() local
171 uint64_t reg_addr; in vf_get_vf_config_mode() local
/dpdk/drivers/net/ngbe/base/
H A Dngbe_phy_yt.c10 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_yt()
37 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_yt()
64 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_ext_yt()
73 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_ext_yt()
82 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_sds_ext_yt()
92 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_sds_ext_yt()
H A Dngbe_phy.c250 s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type, in ngbe_read_phy_reg_mdi()
291 s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr, in ngbe_read_phy_reg()
316 s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, in ngbe_write_phy_reg_mdi()
351 s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr, in ngbe_write_phy_reg()
H A Dngbe_phy_rtl.c8 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_rtl()
24 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_rtl()
H A Dngbe_phy_mvl.c10 u32 reg_addr, u32 device_type, u16 *phy_data) in ngbe_read_phy_reg_mvl()
31 u32 reg_addr, u32 device_type, u16 phy_data) in ngbe_write_phy_reg_mvl()
/dpdk/drivers/raw/ntb/
H A Dntb_hw_intel.c319 void *reg_addr; in intel_ntb_gen3_set_link() local
345 void *reg_addr; in intel_ntb_gen4_set_link() local
409 void *reg_addr; in intel_ntb_spad_read() local
439 void *reg_addr; in intel_ntb_spad_write() local
541 void *reg_addr; in intel_ntb_vector_bind() local
/dpdk/drivers/baseband/fpga_5gnr_fec/
H A Dfpga_5gnr_fec.h299 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8() local
307 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16() local
315 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32() local
323 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64() local
353 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32() local
364 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_16() local
375 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_8() local
383 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_64() local
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_x550.c492 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_phy_reg_x550em()
499 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_x550em()
1102 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_iosf_sb_reg_x550()
1148 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_iosf_sb_reg_x550()
1263 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_iosf_sb_reg_x550a()
1293 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_iosf_sb_reg_x550a()
4349 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_phy_reg_x550a()
4377 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_x550a()
H A Dixgbe_phy.c568 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg_mdi()
650 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_phy_reg_generic()
676 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_mdi()
750 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_generic()
H A Dixgbe_api.c527 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg()
546 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_write_phy_reg()
1260 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_iosf_sb_reg()
1276 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_iosf_sb_reg()
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_phy.c312 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, in txgbe_read_phy_reg_mdi()
352 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr, in txgbe_read_phy_reg()
376 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, in txgbe_write_phy_reg_mdi()
410 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr, in txgbe_write_phy_reg()
/dpdk/drivers/baseband/fpga_lte_fec/
H A Dfpga_lte_fec.c292 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_8() local
300 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_16() local
308 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_32() local
316 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_write_64() local
346 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_32() local
356 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_8() local
364 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_16() local
373 void *reg_addr = RTE_PTR_ADD(mmio_base, offset); in fpga_reg_read_64() local
/dpdk/drivers/net/cxgbe/base/
H A Dadapter.h465 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg()
478 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t4_write_reg()
491 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr, in t4_write_reg_relaxed()
504 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) in t4_read_reg64()
517 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, in t4_write_reg64()
H A Dt4_regs.h7 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) argument
10 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) argument
17 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) argument
20 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) argument
26 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) argument
29 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) argument
33 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) argument
36 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) argument
/dpdk/drivers/net/hinic/base/
H A Dhinic_pmd_api_cmd.c442 u32 reg_addr, val; in api_cmd_hw_restart() local
477 u32 reg_addr, ctrl; in api_cmd_ctrl_init() local
/dpdk/drivers/net/ixgbe/
H A Drte_pmd_ixgbe.c1050 rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr, in rte_pmd_ixgbe_mdio_unlocked_read()
1097 rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr, in rte_pmd_ixgbe_mdio_unlocked_write()
/dpdk/drivers/common/cnxk/
H A Droc_mbox.c271 uintptr_t reg_addr; in mbox_poll() local
/dpdk/drivers/baseband/acc100/
H A Drte_acc100_pmd.c43 void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset); in acc100_reg_write() local
53 void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset); in acc100_reg_read() local
212 const struct acc100_registry_addr *reg_addr; in fetch_acc100_config() local
558 const struct acc100_registry_addr *reg_addr; in allocate_info_ring() local
602 const struct acc100_registry_addr *reg_addr; in acc100_setup_queues() local
/dpdk/drivers/net/i40e/base/
H A Di40e_common.c3576 u32 reg_addr, u64 *reg_val, in i40e_aq_debug_read_register()
3611 u32 reg_addr, u64 reg_val, in i40e_aq_debug_write_register()
7414 u32 reg_addr, u32 *reg_val, in i40e_aq_rx_ctl_read_register()
7442 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) in i40e_read_rx_ctl()
7480 u32 reg_addr, u32 reg_val, in i40e_aq_rx_ctl_write_register()
7504 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) in i40e_write_rx_ctl()
7573 u32 reg_addr, u32 reg_val, in i40e_aq_set_phy_register_ext()
7619 u32 reg_addr, u32 *reg_val, in i40e_aq_get_phy_register_ext()
/dpdk/drivers/crypto/ccp/
H A Dccp_dev.h154 volatile void *reg_addr = ((uint8_t *)base + offset); in ccp_pci_reg_write() local
161 volatile void *reg_addr = ((uint8_t *)base + offset); in ccp_pci_reg_read() local
/dpdk/app/test-pmd/
H A Dtestpmd.h784 void *reg_addr; in port_pci_reg_read() local
813 void *reg_addr; in port_pci_reg_write() local
/dpdk/drivers/net/qede/base/
H A Decore_hw.c317 u32 OSAL_IOMEM *reg_addr; in ecore_memcpy_hw() local
/dpdk/drivers/net/bnx2x/
H A Dbnx2x.c542 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr) in elink_cb_reg_read()
547 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val) in elink_cb_reg_write()
2987 uint32_t reg_addr; in bnx2x_attn_int_asserted() local
4122 uint32_t reg_addr; in bnx2x_attn_int_deasserted() local
10810 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : local
H A Decore_init.h215 uint32_t reg_addr, reg_bit_map, vnic; in ecore_map_q_cos() local
/dpdk/drivers/common/mlx5/linux/
H A Dmlx5_glue.h69 struct mlx5dv_devx_uar { void *reg_addr; void *base_addr; uint32_t page_id; }; member

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