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Searched defs:TSFlags (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h126 static inline unsigned getFormat(uint64_t TSFlags) { in getFormat()
135 static inline VLMUL getLMul(uint64_t TSFlags) { in getLMul()
139 static inline bool hasDummyMaskOp(uint64_t TSFlags) { in hasDummyMaskOp()
143 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { in doesForceTailAgnostic()
147 static inline bool hasMergeOp(uint64_t TSFlags) { in hasMergeOp()
151 static inline bool hasSEWOp(uint64_t TSFlags) { in hasSEWOp()
155 static inline bool hasVLOp(uint64_t TSFlags) { in hasVLOp()
159 static inline bool hasVecPolicyOp(uint64_t TSFlags) { in hasVecPolicyOp()
167 static inline bool usesMaskPolicy(uint64_t TSFlags) { in usesMaskPolicy()
172 const uint64_t TSFlags = Desc.TSFlags; in getVLOpNum() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp121 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8()
144 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind()
322 uint64_t TSFlags, bool HasREX, in emitMemModRMByte()
599 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags; in emitPrefixImpl() local
665 uint64_t TSFlags = Desc.TSFlags; in emitVEXOpcodePrefix() local
1125 uint64_t TSFlags = Desc.TSFlags; in emitREXPrefix() local
1251 uint64_t TSFlags = Desc.TSFlags; in emitOpcodePrefix() local
1311 uint64_t TSFlags = Desc.TSFlags; in emitPrefix() local
1327 uint64_t TSFlags = Desc.TSFlags; in encodeInstruction() local
H A DX86BaseInfo.h974 inline bool isPrefix(uint64_t TSFlags) { in isPrefix()
979 inline bool isPseudo(uint64_t TSFlags) { in isPseudo()
985 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor()
989 inline bool hasImm(uint64_t TSFlags) { in hasImm()
995 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm()
1012 inline bool isImmPCRel(uint64_t TSFlags) { in isImmPCRel()
1031 inline bool isImmSigned(uint64_t TSFlags) { in isImmSigned()
1095 inline int getMemoryOperandNo(uint64_t TSFlags) { in getMemoryOperandNo()
1225 inline bool isKMasked(uint64_t TSFlags) { in isKMasked()
1230 inline bool isKMergeMasked(uint64_t TSFlags) { in isKMergeMasked()
H A DX86InstPrinterCommon.cpp356 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
H A DX86InstComments.cpp263 uint64_t TSFlags = Desc.TSFlags; in printMasking() local
H A DX86AsmBackend.cpp260 uint64_t TSFlags = Desc.TSFlags; in isRIPRelative() local
299 uint64_t TSFlags = Desc.TSFlags; in determinePaddingPrefix() local
H A DX86MCTargetDesc.cpp116 int MemoryOperand, uint64_t TSFlags) { in needsAddressSizeOverride()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp151 uint64_t TSFlags = MI->getDesc().TSFlags; in lowerRISCVVMachineInstrToMCInst() local
H A DRISCVInsertVSETVLI.cpp368 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded() local
776 static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, in computeInfoForInstr()
993 uint64_t TSFlags = MI.getDesc().TSFlags; in transferBefore() local
1203 uint64_t TSFlags = MI.getDesc().TSFlags; in emitVSETVLIs() local
1334 const uint64_t TSFlags = MI.getDesc().TSFlags; in doPRE() local
H A DRISCVInstrInfo.cpp236 uint64_t TSFlags = MBBI->getDesc().TSFlags; in isConvertibleToVMV_V_V() local
1422 uint64_t TSFlags = MI.getDesc().TSFlags; in createMIROperandComment() local
H A DRISCVISelDAGToDAG.cpp2486 uint64_t TSFlags = TII.get(Opc).TSFlags; in doPeepholeMaskedRVV() local
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp141 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group()
H A DX86MCInstLower.cpp974 uint64_t TSFlags = MI->getDesc().TSFlags; in Lower() local
H A DX86InstrInfo.cpp1766 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1, in getThreeSrcCommuteCase()
2312 uint64_t TSFlags = MI.getDesc().TSFlags; in findThreeSrcCommutedOpIndices() local
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYInstPrinter.cpp132 uint64_t TSFlags = MII.get(MI->getOpcode()).TSFlags; in printOperand() local
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp63 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h205 uint64_t TSFlags; // Target Specific Flag values variable
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp575 uint64_t TSFlags = Desc.TSFlags; in evaluateMemoryOperandAddress() local
H A DARMMCCodeEmitter.cpp1871 uint64_t TSFlags = Desc.TSFlags; in encodeInstruction() local
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.h334 uint8_t TSFlags; variable
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3226 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in checkTargetMatchPredicate() local
4048 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateFlatOffset() local
4099 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateSMEMOffset() local
4172 uint64_t TSFlags = MII.get(Opc).TSFlags; in validateOpSel() local
4311 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateAGPRLdSt() local
4445 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateCoherencyBits() local
4496 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; in validateFlatLdsDMA() local
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h62 const uint8_t TSFlags; variable
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp324 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; in decodeOperand_AVLdSt_Any() local

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