| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | VLIWMachineScheduler.h | 40 const TargetSchedModel *SchedModel; variable
128 const TargetSchedModel *SchedModel = nullptr; member
208 const TargetSchedModel *SchedModel = nullptr; variable
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| H A D | TargetSchedule.h | 33 MCSchedModel SchedModel; variable
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| H A D | TargetSubtargetInfo.h | 143 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
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| H A D | ScheduleDAGInstrs.h | 125 TargetSchedModel SchedModel; variable
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| H A D | MachineTraceMetrics.h | 93 TargetSchedModel SchedModel; variable
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| H A D | MachineScheduler.h | 621 const TargetSchedModel *SchedModel = nullptr; variable
911 const TargetSchedModel *SchedModel = nullptr; variable
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.h | 48 const TargetSchedModel *SchedModel; variable
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| H A D | SystemZMachineScheduler.h | 38 TargetSchedModel SchedModel; variable
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 34 TargetSchedModel SchedModel; member in __anone4333b350111::AArch64StorePairSuppress
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| H A D | AArch64ConditionalCompares.cpp | 765 MCSchedModel SchedModel; member in __anoneb5605650211::AArch64ConditionalCompares
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| H A D | AArch64SIMDInstrOpt.cpp | 71 TargetSchedModel SchedModel; member
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| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 59 const MCSchedModel *SchedModel; member
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/ |
| H A D | SchedClassResolution.cpp | 252 const auto &SchedModel = STI.getSchedModel(); in findProcResIdx() local
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 329 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInsertDelayAlu.cpp | 33 TargetSchedModel SchedModel; member in __anond01463870111::AMDGPUInsertDelayAlu
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| H A D | SIInstrInfo.h | 48 TargetSchedModel SchedModel; variable
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 759 MCSchedModel SchedModel; member in __anon1f7aa2560311::EarlyIfConverter
1083 TargetSchedModel SchedModel; member in __anon1f7aa2560911::EarlyIfPredicator
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| H A D | MachineTraceMetrics.cpp | 894 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards()
955 const TargetSchedModel &SchedModel, in pushDepHeight()
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| H A D | MachineCombiner.cpp | 68 MCSchedModel SchedModel; member in __anonec91dd480111::MachineCombiner
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| H A D | TargetInstrInfo.cpp | 1135 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel, in defaultDefLatency()
1161 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
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| H A D | MachineLICM.cpp | 120 TargetSchedModel SchedModel; member in __anonfbf8dede0111::MachineLICMBase
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| H A D | MachineScheduler.cpp | 2019 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init()
2623 const TargetSchedModel *SchedModel) { in initResourceDelta()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 424 bool hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
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| H A D | PPCTargetTransformInfo.cpp | 724 TargetSchedModel SchedModel; in isHardwareLoopProfitable() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.h | 222 MCSchedModel SchedModel; variable
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