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Searched defs:Order (Results 1 – 25 of 87) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAllocationOrderTest.cpp29 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST() local
36 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
43 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST() local
50 SmallVector<MCPhysReg, 16> Order = {4, 5, 6, 7}; in TEST() local
59 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
69 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
76 SmallVector<MCPhysReg, 16> Order = {1, 4, 5, 6}; in TEST() local
83 SmallVector<MCPhysReg, 16> Order = {1, 4, 5, 6}; in TEST() local
92 SmallVector<MCPhysReg, 16> Order = {1, 2, 3, 4}; in TEST() local
101 SmallVector<MCPhysReg, 16> Order = {4, 1, 5, 6}; in TEST() local
/llvm-project-15.0.7/llvm/tools/llvm-tapi-diff/
H A DDiffEngine.cpp24 StringRef setOrderIndicator(InterfaceInputOrder Order) { in setOrderIndicator()
120 InterfaceInputOrder Order) { in addDiffForTargSlice()
139 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
152 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
163 std::string Name, InterfaceInputOrder Order) { in getSingleAttrDiff()
188 const T &Val, InterfaceInputOrder Order) { in diffAttribute()
193 InterfaceInputOrder Order) { in getSingleIF()
234 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
253 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
266 DiffOutput &Result, InterfaceInputOrder Order) { in findAndAddDiff()
H A DDiffEngine.h65 DiffScalarVal(InterfaceInputOrder Order, T Val) in DiffScalarVal()
84 SymScalar(InterfaceInputOrder Order, const MachO::Symbol *Sym) in SymScalar()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder()
H A DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
H A DRegAllocGreedy.cpp365 AllocationOrder &Order, in tryAssign()
419 auto Order = in canReassign() local
498 const AllocationOrder &Order, in getOrderLimit()
544 AllocationOrder &Order, in tryEvict()
1009 AllocationOrder &Order, in tryRegionSplit()
1042 AllocationOrder &Order, in calculateRegionSplitCost()
1174 AllocationOrder &Order, in tryBlockSplit()
1238 AllocationOrder &Order, in tryInstructionSplit()
1381 AllocationOrder &Order, in tryLocalSplit()
1768 AllocationOrder &Order, in tryLastChanceRecoloring()
[all …]
H A DLocalStackSlotAllocation.cpp58 unsigned Order; member in __anon5fe7b08d0111::FrameRef
305 unsigned Order = 0; in insertFrameReferenceRegisters() local
H A DRegAllocBasic.cpp265 auto Order = in selectOrSplit() local
H A DBreakFalseDeps.cpp155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
H A DRegAllocEvictionAdvisor.cpp276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate()
H A DTargetRegisterInfo.cpp251 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
423 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DReorderData.cpp165 DataOrder Order; in baseOrder() local
275 DataOrder Order = baseOrder(BC, Section); in sortedByFunc() local
307 DataOrder Order = baseOrder(BC, Section); in sortedByCount() local
485 DataOrder Order; in runOnFunctions() local
/llvm-project-15.0.7/clang-tools-extra/clangd/unittests/
H A DThreadCrashReporterTests.cpp59 std::string Order = ""; in TEST() local
/llvm-project-15.0.7/llvm/lib/Support/
H A DDynamicLibrary.cpp71 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup()
86 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h149 unsigned Order; variable
245 unsigned Order; variable
H A DScheduleDAGSDNodes.cpp733 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues()
781 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
974 unsigned Order = Orders[i].first; in EmitSchedule() local
1020 unsigned Order = InstrOrder.first; in EmitSchedule() local
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h36 std::unique_ptr<MCPhysReg[]> Order; member
/llvm-project-15.0.7/llvm/unittests/Support/DynamicLibrary/
H A DDynamicLibraryTest.cpp119 std::vector<std::string> Order; in TEST() local
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGOpenMPRuntime.h546 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo()
574 unsigned Order = ~0u; variable
607 explicit OffloadEntryInfoTargetRegion(unsigned Order, in OffloadEntryInfoTargetRegion()
668 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar()
672 unsigned Order, llvm::Constant *Addr, CharUnits VarSize, in OffloadEntryInfoDeviceGlobalVar()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
/llvm-project-15.0.7/llvm/tools/llvm-profgen/
H A DCSPreInliner.cpp76 std::vector<StringRef> Order; in buildTopDownOrder() local
/llvm-project-15.0.7/bolt/lib/Core/
H A DBinarySection.cpp226 void BinarySection::reorderContents(const std::vector<BinaryData *> &Order, in reorderContents()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.h536 unsigned Order = 0; // Cache the sort key. member
778 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt()
782 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt()
/llvm-project-15.0.7/libcxx/benchmarks/algorithms/
H A Dcommon.h32 enum class Order { enum
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DCodeLayout.cpp840 void concatChains(std::vector<uint64_t> &Order) { in concatChains()
933 const std::vector<uint64_t> &Order, const std::vector<uint64_t> &NodeSizes, in calcExtTspScore()
957 auto Order = std::vector<uint64_t>(NodeSizes.size()); in calcExtTspScore() local

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