| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 158 bool IsStore = false; in emitInstruction() local
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess()
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| /llvm-project-15.0.7/bolt/include/bolt/Passes/ |
| H A D | FrameAnalysis.h | 26 bool IsStore; member
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 406 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
455 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kCollapseMOVEMPass.cpp | 204 bool IsStore = false) { in ProcessMI()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1165 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
1202 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
1235 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
1283 bool IsStore = Desc->mayStore(); in buildSpillLoadStore() local
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| H A D | AMDGPULegalizerInfo.cpp | 1133 const bool IsStore = Op == G_STORE; in AMDGPULegalizerInfo() local
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; member
|
| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | X86FoldTablesEmitter.cpp | 108 bool IsStore = false; member in __anone539286b0111::X86FoldTablesEmitter::X86FoldTableEntry
|
| /llvm-project-15.0.7/bolt/lib/Target/X86/ |
| H A D | X86MCPlusBuilder.cpp | 1036 bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore, in isStackAccess()
1077 bool IsStore; in isStackAccess() member
1092 bool IsStore = MCII.mayStore(); in isStackAccess() local
1883 bool IsLoad, IsStore, IsStoreFromReg, IsSimple, IsIndexed; in convertMoveToConditionalMove() local
|
| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | ShrinkWrapping.cpp | 677 bool IsStore = false; in performChanges() local
1553 bool IsStore = false; in insertUpdatedCFI() local
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 467 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
|
| H A D | ARMLoadStoreOptimizer.cpp | 502 bool IsStore = in UpdateBaseRegUses() local
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 823 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
|
| H A D | HexagonConstExtenders.cpp | 1148 bool IsStore = MI.mayStore(); in recordExtender() local
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 383 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
|
| H A D | X86TargetTransformInfo.cpp | 4200 bool IsStore = (Instruction::Store == Opcode); in getMaskedMemoryOpCost() local
|
| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 1344 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
|
| /llvm-project-15.0.7/bolt/include/bolt/Core/ |
| H A D | MCPlusBuilder.h | 897 virtual bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore, in isStackAccess()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2872 bool IsStore = isa<GStore>(I); in select() local
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1055 bool IsStore = Opcode == TargetOpcode::G_STORE; in applyCombineIndexedLoadStore() local
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17823 bool IsStore = false; in performNEONPostLDSTCombine() local
|