| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | SCCP.cpp | 172 Value *ExtOp = Inst.getOperand(0); in simplifyInstsInBlock() local
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 4570 unsigned ExtOp, TruncOp; in PromoteNode() local
4603 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND in PromoteNode() local
4619 unsigned ExtOp, TruncOp; in PromoteNode() local
4674 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
4707 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
4734 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
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| H A D | DAGCombiner.cpp | 15707 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 1889 unsigned ExtOp = in getTypeBasedIntrinsicInstrCost() local
1955 unsigned ExtOp = IsSigned ? Instruction::SExt : Instruction::ZExt; in getTypeBasedIntrinsicInstrCost() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 435 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
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| H A D | SIISelLowering.cpp | 10369 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 472 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt() local
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| H A D | LegalizerHelper.cpp | 1910 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); in widenScalarAddSubOverflow() local
1986 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in widenScalarMulo() local
7200 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in lowerSMULH_UMULH() local
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyIndVar.cpp | 1499 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstExtenders.cpp | 1535 MachineOperand ExtOp(EV); in insertInitializer() local
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6194 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
14262 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 6781 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op); in combineINT_TO_FP() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 19886 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
41438 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
41470 SDValue ExtOp = in SimplifyDemandedVectorEltsForTargetNode() local
41513 SDValue ExtOp = TLO.DAG.getNode(Opc, DL, ExtVT, Ops); in SimplifyDemandedVectorEltsForTargetNode() local
54528 unsigned ExtOp = getOpcode_EXTEND_VECTOR_INREG(InOpcode); in combineEXTRACT_SUBVECTOR() local
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 7270 Value *ExtOp, Value *IndexOp, in packTBLDVectorList()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19155 SDValue ExtOp = Src->getOperand(0); in performSignExtendInRegCombine() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 12576 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
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