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Searched defs:ExtOp (Results 1 – 10 of 10) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4209 unsigned ExtOp, TruncOp; in PromoteNode() local
4242 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND in PromoteNode() local
4258 unsigned ExtOp, TruncOp; in PromoteNode() local
4298 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
4311 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode() local
H A DDAGCombiner.cpp12039 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUCodeGenPrepare.cpp383 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
H A DSIISelLowering.cpp8038 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1533 MachineOperand ExtOp(EV); in insertInitializer() local
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DIndVarSimplify.cpp1349 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5818 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
6381 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
12217 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGBuiltin.cpp5629 Value *ExtOp, Value *IndexOp, in packTBLDVectorList()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9958 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp16513 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
33737 SDValue ExtOp = DAG.getNode(OpCode, dl, MVT::i32, SrcOp, in combineExtractWithShuffle() local
41414 unsigned ExtOp = in combineExtractSubvector() local