| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FlagsCopyLowering.cpp | 771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
854 unsigned CondReg; in rewriteCMov() local
880 unsigned CondReg; in rewriteFCMov() local
922 unsigned CondReg; in rewriteCondJmp() local
958 unsigned &CondReg = CondRegs[Cond]; in rewriteSetCC() local
|
| H A D | X86FastISel.cpp | 2115 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2315 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
|
| H A D | X86InstructionSelector.cpp | 1365 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 90 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
|
| H A D | SIOptimizeExecMaskingPreRA.cpp | 39 MCRegister CondReg; member in __anon6b0c42990111::SIOptimizeExecMaskingPreRA
|
| H A D | SIInstrInfo.cpp | 2642 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags()
2698 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
5493 Register CondReg = AMDGPU::NoRegister; in emitLoadSRsrcFromVGPRLoop() local
6183 Register CondReg = Inst.getOperand(1).getReg(); in moveToVALU() local
6320 Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass()); in moveToVALU() local
|
| H A D | AMDGPURegisterBankInfo.cpp | 843 Register CondReg; in executeInWaterfallLoop() local
2269 Register CondReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
|
| H A D | AMDGPUISelDAGToDAG.cpp | 2264 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
|
| H A D | AMDGPUMachineCFGStructurizer.cpp | 1848 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
|
| H A D | AMDGPUInstructionSelector.cpp | 2480 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
|
| H A D | SIISelLowering.cpp | 3601 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
|
| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 913 unsigned CondReg = in selectSelect() local
1314 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); in selectBr() local
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 961 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
1040 Register CondReg = getRegForValue(Cond); in selectSelect() local
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2457 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2471 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2693 Register CondReg = getRegForValue(Cond); in selectSelect() local
2742 Register CondReg = getRegForValue(Cond); in selectSelect() local
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 774 auto CondReg = MIB.getReg(1); in selectSelect() local
|
| H A D | ARMFastISel.cpp | 1610 Register CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 786 Register CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1711 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
3344 const Register CondReg = Sel.getCondReg(); in select() local
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 4865 Register CondReg = MI.getOperand(1).getReg(); in moreElementsVector() local
5402 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
|