| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 298 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
354 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
460 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.h | 37 Register BaseReg; member
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 462 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
514 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
573 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
766 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
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| H A D | X86AsmPrinter.cpp | 289 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
385 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| H A D | X86InsertPrefetch.cpp | 83 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64StorePairSuppress.cpp | 156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| H A D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| H A D | AArch64RegisterInfo.cpp | 600 Register BaseReg, in isFrameOffsetLegal()
622 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
634 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | AArch64LoadStoreOptimizer.cpp | 1223 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1520 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1854 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1910 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1988 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
441 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | Thumb2SizeReduction.cpp | 500 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
530 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
538 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
551 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| H A D | ARMBaseRegisterInfo.cpp | 681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
722 Register BaseReg, in isFrameOffsetLegal()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 272 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
346 Register BaseReg; in insertFrameReferenceRegisters() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 75 SDValue &BaseReg, in SelectGlobalValueVariableOffset()
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 273 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
338 BitVector &CandidateDestRegs) { in generateCodeTemplates()
398 BitVector &CandidateDestRegs) { in generateCodeTemplates()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86ATTInstPrinter.cpp | 426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| H A D | X86IntelInstPrinter.cpp | 383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| H A D | X86MCTargetDesc.cpp | 649 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress() local
675 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | JTFootprintReduction.cpp | 175 MCPhysReg BaseReg; in tryOptimizePIC() local
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 374 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
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| /llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 297 const MemRegion *BaseReg = MRMgr.getCXXBaseObjectRegion( in evalDerivedToBase() local
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 1764 Register BaseReg = MRI.createVirtualRegister(RC); in materializeFrameBaseRegister() local
1773 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
1798 Register BaseReg, in isFrameOffsetLegal()
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