lspci: Add test case for CXL device

Add requested config space dump of CXL device for testing

Signed-off-by: Jaxon Haws <[email protected]>

lspci: Update tests files with VF 10-Bit Tag Requester

Update the tests files with the new field 10BitTagReq
in SR-IOV Capabilities Register.

Signed-off-by: Dongdong Liu <[email protected]>

CXL: Capability vendor ID changed

Update the cap-dvsec-cxl test to match the new vendor ID.

Signed-off-by: Sean V Kelley <[email protected]>

Tests: cap-dvsec-cxl had tabs erroneously expanded to spaces

pciutils: Decode Compute eXpress Link DVSEC

Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical inte

pciutils: Decode Compute eXpress Link DVSEC

Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical interconnect for communication via a Flex Bus
port which allows designs to choose between providing PCIe or CXL.

This patch introduces basic support for lspci decode of CXL and
builds upon the existing Designated Vendor-Specific support in
lspci through identification of a supporting CXL device using DVSEC
Vendor ID and DVSEC ID.

[1] https://www.computeexpresslink.org/

Signed-off-by: Sean V Kelley <[email protected]>

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