Oops. Forgot these.

llvm-svn: 44969

Add a flag for indirect branch instructions.

Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012

Add sqrt and powi intrinsics for long double.

llvm-svn: 42423

Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.

llvm-svn: 42123

Add MVT::fAny for overloading intrinsics on floating-point types.

llvm-svn: 41128

This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It

This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.

This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807

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Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350

llvm-svn: 40518

Teach TableGen about the new vector types.

llvm-svn: 40513

No need for noResults anymore.

llvm-svn: 40075

Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the ch

Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

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Eliminate an unused parameter.

llvm-svn: 39828

Try committing again. Add OptionalDefOperand. Remove clobbersPred.

llvm-svn: 38498

ImmutablePredicateOperand is no more.

llvm-svn: 37963

Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.

llvm-svn: 37899

Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions th

Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

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Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with speci

Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

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Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.

llvm-svn: 37643

Add support to tablegen for specifying subregister classes on a per register class basis.

llvm-svn: 37572

Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.

llvm-svn: 37465

Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
being changed from an enum to an integer type, which can't have a custom
operator<< overload.

llvm-svn: 37412

Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.

llvm-svn: 37116

For PR1297:
Implement code generation for overloaded intrinsic functions. The basic
difference is that "actual" argument types must be provided when
constructing intrinsic names and types. Also, for

For PR1297:
Implement code generation for overloaded intrinsic functions. The basic
difference is that "actual" argument types must be provided when
constructing intrinsic names and types. Also, for recognition, only the
prefix is examined. If it matches, the suffix is assumed to match. The
suffix is checked by the Verifier, however.

llvm-svn: 35539

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Add support for the v1i64 type. This makes better code for this:

#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}

We get this:

_baz:
call

Add support for the v1i64 type. This makes better code for this:

#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}

We get this:

_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret

GCC gives us this:

_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret

llvm-svn: 35351

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Recognize target instruction flag 'isReMaterializable'.

llvm-svn: 35159

reapply

llvm-svn: 34697