Lower stackmap intrinsics directly to their target opcode in the DAG builder.

llvm-svn: 193769

Add v4f16 to supported value types.

This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.

llvm-svn: 191870

Initial support for Neon scalar instructions.

Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arit

Initial support for Neon scalar instructions.

Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263

show more ...

[Mips][msa] Value types for MSA support.

Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td,
and CodeGenTarget.cpp

Patch by Daniel Sanders

llvm-svn: 188326

Add 'const' qualifier to some arrays.

llvm-svn: 186312

Extend 'readonly' and 'readnone' to work on function arguments as well as
functions. Make the function attributes pass add it to known library functions
and when it can deduce it.

llvm-svn: 185735

Use ArrayRef<MVT::SimpleValueType> when possible.

Not passing vector references around makes it possible to use
SmallVector in most places.

llvm-svn: 177235

Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64

llvm-svn: 171026

Sort the #include lines for utils/...

I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251

Remove exception handling usage from tblgen.

Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenD

Remove exception handling usage from tblgen.

Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set.

llvm-svn: 166712

show more ...

Add in new data types that are used by AMDIL/ANL among others.

llvm-svn: 164261

Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.

llvm-svn: 163659

Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX in

Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).

llvm-svn: 163299

show more ...

Add CodeGenTarget::guessInstructionProperties.

Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the ins

Add CodeGenTarget::guessInstructionProperties.

Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

llvm-svn: 162460

show more ...

I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic proper

I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891

show more ...

whitespace

llvm-svn: 159890

rdar://11542750 - llvm.trap should be marked no return.

llvm-svn: 157551

Revert "Emit the SubRegTable with the smallest possible integer type."

This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type

Revert "Emit the SubRegTable with the smallest possible integer type."

This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

llvm-svn: 151814

show more ...

Emit the SubRegTable with the smallest possible integer type.

Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

llvm-svn: 151760

Convert assert(0) to llvm_unreachable

llvm-svn: 149814

Added MVT::v2f16

llvm-svn: 148067

Split AsmParser into two components - AsmParser and AsmParserVariant

AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.

ll

Split AsmParser into two components - AsmParser and AsmParserVariant

AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.

llvm-svn: 147787

show more ...

Add basic generic CodeGen support for half.

llvm-svn: 146927

First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an itera

First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975

show more ...

Rename MVT::untyped to MVT::Untyped to match similar nomenclature.

llvm-svn: 144747