[IR] Move vector.insert/vector.extract out of experimental namespace

These intrinsics are now fundemental for SVE code generation and have been
present for a year and a half, hence move them out of

[IR] Move vector.insert/vector.extract out of experimental namespace

These intrinsics are now fundemental for SVE code generation and have been
present for a year and a half, hence move them out of the experimental
namespace.

Differential Revision: https://reviews.llvm.org/D127976

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[Aarch64] Remove redundant declaration initializeSVEIntrinsicOptsPass (NFC)

The function is declared in AArch64.h.

Identified with readability-redundant-declaration.

[llvm] Strip redundant lambda (NFC)

[IR] Split vscale_range interface

Interface is split from:

std::pair<unsigned, unsigned> getVScaleRangeArgs()

into separate functions for min/max:

unsigned getVScaleRangeMin();
Optional<uns

[IR] Split vscale_range interface

Interface is split from:

std::pair<unsigned, unsigned> getVScaleRangeArgs()

into separate functions for min/max:

unsigned getVScaleRangeMin();
Optional<unsigned> getVScaleRangeMax();

Reviewed By: sdesmalen, paulwalker-arm

Differential Revision: https://reviews.llvm.org/D114075

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[llvm][clang][NFC] updates inline licence info

Some files still contained the old University of Illinois Open Source
Licence header. This patch replaces that with the Apache 2 with LLVM
Exception li

[llvm][clang][NFC] updates inline licence info

Some files still contained the old University of Illinois Open Source
Licence header. This patch replaces that with the Apache 2 with LLVM
Exception licence.

Differential Revision: https://reviews.llvm.org/D107528

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[AArch64][SVE] Combine bitcasts of predicate types with vector inserts/extracts of loads/stores

An insert subvector that is inserting the result of a vector predicate
sized load into undef at index

[AArch64][SVE] Combine bitcasts of predicate types with vector inserts/extracts of loads/stores

An insert subvector that is inserting the result of a vector predicate
sized load into undef at index 0, whose result is casted to a predicate
type, can be combined into a direct predicate load. Likewise the same
applies to extract subvector but in reverse.

The purpose of this optimization is to clean up cases that will be
introduced in a later patch where casts to/from predicate types from i8
types will use insert subvector, rather than going through memory early.

This optimization is done in SVEIntrinsicOpts rather than InstCombine to
re-introduce scalable loads as late as possible, to give other
optimizations the best chance possible to do a good job.

Differential Revision: https://reviews.llvm.org/D106549

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[AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts

Instead move them to the instcombine that happens in AArch64TargetTransformInfo.

Differential Revision: https://reviews.llvm.

[AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts

Instead move them to the instcombine that happens in AArch64TargetTransformInfo.

Differential Revision: https://reviews.llvm.org/D106144

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[AArch64] Fix namespace issue. NFC

[AArch64][SVE] Remove unused function missed from D101302

The functionality in SVEIntrinsicOpts::isReinterpretToSVBool was moved in
D101302, however the original now unused function was not removed

[AArch64][SVE] Remove unused function missed from D101302

The functionality in SVEIntrinsicOpts::isReinterpretToSVBool was moved in
D101302, however the original now unused function was not removed (NFC).

Differential Revision: https://reviews.llvm.org/D101642

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[AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine

As part of this the ptrue coalescing done in SVEIntrinsicOpts has been
modified to not introduce redundant converts, since

[AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine

As part of this the ptrue coalescing done in SVEIntrinsicOpts has been
modified to not introduce redundant converts, since the convert removal
will no longer run after that optimisation to clean up.

Differential Revision: https://reviews.llvm.org/D101302

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[AArch64][SVEIntrinsicOpts] Optimize tbl+dup into dup+extractelement

Differential Revision: https://reviews.llvm.org/D99412

[AArch64][SVEIntrinsicOpts] Factor out redundant SVE mul/fmul intrinsics

This commit implements an IR-level optimization to eliminate idempotent
SVE mul/fmul intrinsic calls. Currently, the followin

[AArch64][SVEIntrinsicOpts] Factor out redundant SVE mul/fmul intrinsics

This commit implements an IR-level optimization to eliminate idempotent
SVE mul/fmul intrinsic calls. Currently, the following patterns are
captured:

fmul pg (dup_x 1.0) V => V
mul pg (dup_x 1) V => V

fmul pg V (dup_x 1.0) => V
mul pg V (dup_x 1) => V

fmul pg V (dup v pg 1.0) => V
mul pg V (dup v pg 1) => V

The result of this commit is that code such as:

1 #include <arm_sve.h>
2
3 svfloat64_t foo(svfloat64_t a) {
4 svbool_t t = svptrue_b64();
5 svfloat64_t b = svdup_f64(1.0);
6 return svmul_m(t, a, b);
7 }

will lower to a nop.

This commit does not capture all possibilities; only the simple cases
described above. There is still room for further optimisation.

Differential Revision: https://reviews.llvm.org/D98033

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[AArch64][SVE] Coalesce ptrue instrinsic calls where possible

It is possible to eliminate redundant calls to the SVE ptrue intrinsic.
For example: suppose that we have two SVE ptrue intrinsic calls

[AArch64][SVE] Coalesce ptrue instrinsic calls where possible

It is possible to eliminate redundant calls to the SVE ptrue intrinsic.
For example: suppose that we have two SVE ptrue intrinsic calls P1 and
P2. If P1 is at least as wide as P2, then P2 can be written as a
reinterpret P1 using the SVE reinterpret intrinsics.

Coalescing ptrue intrinsics can result in fewer ptrue instructions in
the codegen, and is conducive to better analysis further down the line.

This commit extends the aarch64-sve-intrinsic-opts pass to support
coalescing ptrue intrisic calls.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D94230

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[AArch64][SVE] Remove chains of unnecessary SVE reinterpret intrinsics

This commit extends SVEIntrinsicOpts::optimizeConvertFromSVBool to
identify and remove longer chains of redundant SVE reintepre

[AArch64][SVE] Remove chains of unnecessary SVE reinterpret intrinsics

This commit extends SVEIntrinsicOpts::optimizeConvertFromSVBool to
identify and remove longer chains of redundant SVE reintepret
intrinsics. For example, the following chain of redundant SVE
reinterprets is now recognised as redundant:

%a = <vscale x 2 x i1>
%1 = <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool(<vscale x 2 x i1> %a)
%2 = <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool(<vscale x 16 x i1> %1)
%3 = <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool(<vscale x 4 x i1> %2)
%4 = <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool(<vscale x 16 x i1> %3)
%5 = <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool(<vscale x 4 x i1> %4)
%6 = <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool(<vscale x 16 x i1> %5)
ret <vscale x 2 x i1> %6

and will be replaced with:

ret <vscale x 2 x i1> %a

Eliminating these can sometimes mean emitting fewer unnecessary
loads/stores when lowering to assembly.

Differential Revision: https://reviews.llvm.org/D94074

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[AArch64] SVEIntrinsicOpts - use range loop and cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.

Don't directly dereference a dyn_cast<> - use cast<> so we assert for the correct type.

[AArch64] SVEIntrinsicOpts - use range loop and cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.

Don't directly dereference a dyn_cast<> - use cast<> so we assert for the correct type.

Also, simplify the for loop to a range loop.

Fixes clang static analyzer warning.

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[SVE] Fix bug in SVEIntrinsicOpts::optimizePTest

The code wasn't taking into account that the two operands
passed to ptest could be identical and was trying to erase
them twice.

Differential Revisi

[SVE] Fix bug in SVEIntrinsicOpts::optimizePTest

The code wasn't taking into account that the two operands
passed to ptest could be identical and was trying to erase
them twice.

Differential Revision: https://reviews.llvm.org/D85892

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Prefix some AArch64/ARM passes with "aarch64-"/"arm-"

For consistency with other target specific passes.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D84560

[SVEIntrinsicOpts] NFC: Remove unused isReinterpretFromBool for no-assert builds

isReinterpretFromBool's only use is in an assert, which causes a warning that the
function is defined but not used in

[SVEIntrinsicOpts] NFC: Remove unused isReinterpretFromBool for no-assert builds

isReinterpretFromBool's only use is in an assert, which causes a warning that the
function is defined but not used in no-assert builds.

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[AArch64][SVE] Add a pass for SVE intrinsic optimisations

Summary:
Creates the SVEIntrinsicOpts pass. In this patch, the pass tries
to remove unnecessary reinterpret intrinsics which convert to
and

[AArch64][SVE] Add a pass for SVE intrinsic optimisations

Summary:
Creates the SVEIntrinsicOpts pass. In this patch, the pass tries
to remove unnecessary reinterpret intrinsics which convert to
and from svbool_t (llvm.aarch64.sve.convert.[to|from].svbool)

For example, the reinterprets below are redundant:

%1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %a)
%2 = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %1)

The pass also looks for ptest intrinsics and phi instructions where
the operands are being needlessly converted to and from svbool_t.

Reviewers: sdesmalen, andwar, efriedma, cameron.mcinally, c-rhodes, rengolin

Reviewed By: efriedma

Subscribers: mgorny, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76078

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