[BOLT][AArch64] Handle gold linker veneersThe gold linker veneers are written between functions without symbols,so we to handle it specially in BOLT.Vladislav Khmelevsky,Advanced Software Techn
[BOLT][AArch64] Handle gold linker veneersThe gold linker veneers are written between functions without symbols,so we to handle it specially in BOLT.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D129260
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Revert "[BOLT][AArch64] Handle gold linker veneers"This reverts commit 425dda76e9fac93117289fd68a2abdfb1e4a0ba5.This commit is currently causing BOLT to crash in one of ourbinaries and needs a b
Revert "[BOLT][AArch64] Handle gold linker veneers"This reverts commit 425dda76e9fac93117289fd68a2abdfb1e4a0ba5.This commit is currently causing BOLT to crash in one of ourbinaries and needs a bit more checking to make sure it is safeto land.
[BOLT][AArch64] Handle gold linker veneersThe gold linker veneers are written between functions without symbols,so we to handle it specially in BOLT.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D128082
[BOLT][NFC] Suppress unused variable warningsAddress warnings in Release build without assertions.Tip @tschuett for reporting the issue #55404.Reviewed By: rafaulerDifferential Revision: https
[BOLT][NFC] Suppress unused variable warningsAddress warnings in Release build without assertions.Tip @tschuett for reporting the issue #55404.Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D125475
[BOLT][NFC] Use BitVector::set_bitsRefactor and use `set_bits` BitVector interface.Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D125374
[BOLT][NFC] Add MCPlus::primeOperands iterator_rangeReviewed By: yota9Differential Revision: https://reviews.llvm.org/D125397
[BOLT][NFC] Reduce Target/{AArch64,X86} dependenciesWe don't actually depend on entire X86/AArch64 components that pull in CodeGen,SelectionDAG etc., just the Desc part with opcode and other defin
[BOLT][NFC] Reduce Target/{AArch64,X86} dependenciesWe don't actually depend on entire X86/AArch64 components that pull in CodeGen,SelectionDAG etc., just the Desc part with opcode and other definitions.Note that it doesn't decouple BOLT from these components - we still pull in X86and AArch64 from top-level llvm-bolt dependencies as we use assembler anddisassembler. It's difficult to reduce these as this requires non-trivialchanges to X86/AArch64 components themselves (e.g. moving out AsmPrinter).Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D124206
[BOLT][NFC] Move isADD64rr and isADDri out of MCPlusBuilder classReviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D123077
[BOLT] Strip redundant AdSize override prefixSince LLVM MC now preserves redundant AdSize override prefix (0x67), remove itin BOLT explicitly (-x86-strip-redundant-adsize, on by default).Test Pl
[BOLT] Strip redundant AdSize override prefixSince LLVM MC now preserves redundant AdSize override prefix (0x67), remove itin BOLT explicitly (-x86-strip-redundant-adsize, on by default).Test Plan:`bin/llvm-lit -a bolt/test/X86/addr32.s`Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D120975
[BOLT][NFC] Return MCRegister::NoRegister from MCPlusBuilder::getNoRegister()Reviewed By: yota9Differential Revision: https://reviews.llvm.org/D120863
[BOLT] Enable PLT analysis for aarch64This patch enables PLT analysis for aarch64. It is used by the staticrelocations in order to provide final symbol address of PLT entry for someinstructions l
[BOLT] Enable PLT analysis for aarch64This patch enables PLT analysis for aarch64. It is used by the staticrelocations in order to provide final symbol address of PLT entry for someinstructions like ADRP.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D118088
[BOLT] Add aarch64 support for peephole passesEnable peephole optimizations for aarch64.Also small code refactoring - add PeepholeOpts under Peepholes class.Vladislav Khmelevsky,Advanced Softwa
[BOLT] Add aarch64 support for peephole passesEnable peephole optimizations for aarch64.Also small code refactoring - add PeepholeOpts under Peepholes class.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D118732
[BOLT][NFC] Move Offset annotation to Group 1Summary:Move the annotation to avoid dynamic memory allocations.Improves the CPU time of instrumenting a large binary by 1% (+-0.8%, p-value 0.01)Te
[BOLT][NFC] Move Offset annotation to Group 1Summary:Move the annotation to avoid dynamic memory allocations.Improves the CPU time of instrumenting a large binary by 1% (+-0.8%, p-value 0.01)Test Plan: NFCReviewers: maksfbFBD30091656
[BOLT][NFC] Refactor AArch64MCPlusBuilderSummary: Selectively apply clang-format to the code in AArch64MCPlusBuilder.cpp.(cherry picked from FBD33495653)
[BOLT][NFC] Use uniform DEBUG_TYPE for MCPlus builders(cherry picked from FBD33435121)
[BOLT][NFC] Fix braces usage in TargetSummary:Refactor bolt/lib/Target to follow the braces rule for if/else/loop from[LLVM Coding Standards](https://llvm.org/docs/CodingStandards.html).(cherry
[BOLT][NFC] Fix braces usage in TargetSummary:Refactor bolt/lib/Target to follow the braces rule for if/else/loop from[LLVM Coding Standards](https://llvm.org/docs/CodingStandards.html).(cherry picked from FBD33345353)
[BOLT][NFC] Fix file-description commentsSummary: Fix comments at the start of source files.(cherry picked from FBD33274597)
[BOLT][NFC] Reformat with clang-formatSummary: Selectively apply clang-format to BOLT code base.(cherry picked from FBD33119052)
[BOLT] Refactor BinaryBasicBlock to use ADTSummary:Refactor members of BinaryBasicBlock. Replace some std containers withADT equivalents. The size of BinaryBasicBlock on x86-64 Linux is reducedf
[BOLT] Refactor BinaryBasicBlock to use ADTSummary:Refactor members of BinaryBasicBlock. Replace some std containers withADT equivalents. The size of BinaryBasicBlock on x86-64 Linux is reducedfrom 232 bytes to 192 bytes.(cherry picked from FBD33081850)
Rebase: [NFC] Refactor sources to be buildable in shared modeSummary:Moves source files into separate components, and make explicitcomponent dependency on each other, so LLVM build system knows h
Rebase: [NFC] Refactor sources to be buildable in shared modeSummary:Moves source files into separate components, and make explicitcomponent dependency on each other, so LLVM build system knows how tobuild BOLT in BUILD_SHARED_LIBS=ON.Please use the -c merge.renamelimit=230 git option when rebasing yourwork on top of this change.To achieve this, we create a new library to hold core IR files (mostclasses beginning with Binary in their names), a new library to holdUtils, some command line options shared across both RewriteInstanceand core IR files, a new library called Rewrite to hold most classesconcerned with running top-level functions coordinating the binaryrewriting process, and a new library called Profile to hold classesdealing with profile reading and writing.To remove the dependency from BinaryContext into X86-specific classes,we do some refactoring on the BinaryContext constructor to receive areference to the specific backend directly from RewriteInstance. Then,the dependency on X86 or AArch64-specific classes is transfered to theRewrite library. We can't have the Core library depend on targetsbecause targets depend on Core (which would create a cycle).Files implementing the entry point of a tool are transferred to thetools/ folder. All header files are transferred to the include/folder. The src/ folder was renamed to lib/.(cherry picked from FBD32746834)