KVM: riscv: selftests: Add helper functions for extension checks

__vcpu_has_ext can check both SBI and ISA extensions when the first
argument is properly converted to SBI/ISA extension IDs. Introduc

KVM: riscv: selftests: Add helper functions for extension checks

__vcpu_has_ext can check both SBI and ISA extensions when the first
argument is properly converted to SBI/ISA extension IDs. Introduce
two helper functions to make life easier for developers so they
don't have to worry about the conversions.

Replace the current usages as well with new helpers.

Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Move sbi definitions to its own header file

The SBI definitions will continue to grow. Move the sbi related
definitions to its own header file from processor.h

Suggested-by:

KVM: riscv: selftests: Move sbi definitions to its own header file

The SBI definitions will continue to grow. Move the sbi related
definitions to its own header file from processor.h

Suggested-by: Andrew Jones <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Add sstc timer test

Add a KVM selftests to validate the Sstc timer functionality.
The test was ported from arm64 arch timer test.

Signed-off-by: Haibo Xu <[email protected]

KVM: riscv: selftests: Add sstc timer test

Add a KVM selftests to validate the Sstc timer functionality.
The test was ported from arm64 arch timer test.

Signed-off-by: Haibo Xu <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Change vcpu_has_ext to a common function

Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext
so that other test cases can use it for vCPU extension check.

Si

KVM: riscv: selftests: Change vcpu_has_ext to a common function

Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext
so that other test cases can use it for vCPU extension check.

Signed-off-by: Haibo Xu <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Add exception handling support

Add the infrastructure for guest exception handling in riscv selftests.
Customized handlers can be enabled by vm_install_exception_handler(vecto

KVM: riscv: selftests: Add exception handling support

Add the infrastructure for guest exception handling in riscv selftests.
Customized handlers can be enabled by vm_install_exception_handler(vector)
or vm_install_interrupt_handler().

The code is inspired from that of x86/arm64.

Signed-off-by: Haibo Xu <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Switch to use macro from csr.h

Signed-off-by: Haibo Xu <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

RISC-V: KVM: selftests: Add steal_time test support

With the introduction of steal-time accounting support for
RISC-V KVM we can add RISC-V support to the steal_time test.

Reviewed-by: Anup Patel <

RISC-V: KVM: selftests: Add steal_time test support

With the introduction of steal-time accounting support for
RISC-V KVM we can add RISC-V support to the steal_time test.

Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Signed-off-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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RISC-V: KVM: selftests: Add guest_sbi_probe_extension

Add guest_sbi_probe_extension(), allowing guest code to probe for
SBI extensions. As guest_sbi_probe_extension() needs
SBI_ERR_NOT_SUPPORTED, ta

RISC-V: KVM: selftests: Add guest_sbi_probe_extension

Add guest_sbi_probe_extension(), allowing guest code to probe for
SBI extensions. As guest_sbi_probe_extension() needs
SBI_ERR_NOT_SUPPORTED, take the opportunity to bring in all SBI
error codes. We don't bring in all current extension IDs or base
extension function IDs though, even though we need one of each,
because we'd prefer to bring those in as necessary.

Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Signed-off-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Add RISCV_SBI_EXT_REG

While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macro

KVM: riscv: selftests: Add RISCV_SBI_EXT_REG

While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macros to set the new field appropriately. The
general CSR macro gets renamed to include "GENERAL", but the other
macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype.

Signed-off-by: Andrew Jones <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: riscv: selftests: Add get-reg-list test

get-reg-list test is used to check for KVM registers regressions
during VM migration which happens when destination host kernel
missing registers that th

KVM: riscv: selftests: Add get-reg-list test

get-reg-list test is used to check for KVM registers regressions
during VM migration which happens when destination host kernel
missing registers that the source host kernel has. The blessed
list registers was created by running on v6.5-rc3

Signed-off-by: Haibo Xu <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: selftests: Consolidate KVM_{G,S}ET_ONE_REG helpers

Rework vcpu_{g,s}et_reg() to provide the APIs that tests actually want to
use, and drop the three "one-off" implementations that cropped up du

KVM: selftests: Consolidate KVM_{G,S}ET_ONE_REG helpers

Rework vcpu_{g,s}et_reg() to provide the APIs that tests actually want to
use, and drop the three "one-off" implementations that cropped up due to
the poor API.

Ignore the handful of direct KVM_{G,S}ET_ONE_REG calls that don't fit the
APIs for one reason or another.

No functional change intended.

Signed-off-by: Sean Christopherson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

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KVM: selftests: riscv: Improve unexpected guest trap handling

Currently, we simply hang using "while (1) ;" upon any unexpected
guest traps because the default guest trap handler is guest_hang().

T

KVM: selftests: riscv: Improve unexpected guest trap handling

Currently, we simply hang using "while (1) ;" upon any unexpected
guest traps because the default guest trap handler is guest_hang().

The above approach is not useful to anyone because KVM selftests
users will only see a hung application upon any unexpected guest
trap.

This patch improves unexpected guest trap handling for KVM RISC-V
selftests by doing the following:
1) Return to host user-space
2) Dump VCPU registers
3) Die using TEST_ASSERT(0, ...)

Signed-off-by: Anup Patel <[email protected]>
Tested-by: Mayuresh Chitale <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table

Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always

KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table

Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always set
these bits in both G-stage (hypervisor) and VS-stage (guest kernel).

If PTE A and D bits are not set by software (hypervisor or guest)
then RISC-V implementations not supporting hardware updates of these
bits will cause traps even for perfectly valid PTEs.

Based on above explanation, the VS-stage page table created by various
KVM selftest applications is not correct because PTE A and D bits are
not set. This patch fixes VS-stage page table programming of PTE A and
D bits for KVM selftests.

Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel <[email protected]>
Tested-by: Mayuresh Chitale <[email protected]>
Signed-off-by: Anup Patel <[email protected]>

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KVM: selftests: Add initial support for RISC-V 64-bit

We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging

KVM: selftests: Add initial support for RISC-V 64-bit

We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging_test
dirty_log_test
kvm_create_max_vcpus,
kvm_page_table_test
set_memory_region_test
kvm_binary_stats_test

All VM guest modes defined in kvm_util.h require at least 48-bit
guest virtual address so to use KVM RISC-V selftests hardware
need to support at least Sv48 MMU for guest (i.e. VS-mode).

Signed-off-by: Anup Patel <[email protected]>
Reviewed-and-tested-by: Atish Patra <[email protected]>

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