1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RISC-V processor specific defines 4 * 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 */ 7 #ifndef SELFTEST_KVM_PROCESSOR_H 8 #define SELFTEST_KVM_PROCESSOR_H 9 10 #include <linux/stringify.h> 11 #include <asm/csr.h> 12 #include "kvm_util.h" 13 14 static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype, 15 uint64_t idx, uint64_t size) 16 { 17 return KVM_REG_RISCV | type | subtype | idx | size; 18 } 19 20 #if __riscv_xlen == 64 21 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64 22 #else 23 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 24 #endif 25 26 #define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \ 27 KVM_REG_RISCV_CONFIG_REG(name), \ 28 KVM_REG_SIZE_ULONG) 29 30 #define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, 0, \ 31 KVM_REG_RISCV_CORE_REG(name), \ 32 KVM_REG_SIZE_ULONG) 33 34 #define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ 35 KVM_REG_RISCV_CSR_GENERAL, \ 36 KVM_REG_RISCV_CSR_REG(name), \ 37 KVM_REG_SIZE_ULONG) 38 39 #define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, 0, \ 40 KVM_REG_RISCV_TIMER_REG(name), \ 41 KVM_REG_SIZE_U64) 42 43 #define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ 44 KVM_REG_RISCV_ISA_SINGLE, \ 45 idx, KVM_REG_SIZE_ULONG) 46 47 #define RISCV_SBI_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_SBI_EXT, \ 48 KVM_REG_RISCV_SBI_SINGLE, \ 49 idx, KVM_REG_SIZE_ULONG) 50 51 /* L3 index Bit[47:39] */ 52 #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL 53 #define PGTBL_L3_INDEX_SHIFT 39 54 #define PGTBL_L3_BLOCK_SHIFT 39 55 #define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL 56 #define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1)) 57 /* L2 index Bit[38:30] */ 58 #define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL 59 #define PGTBL_L2_INDEX_SHIFT 30 60 #define PGTBL_L2_BLOCK_SHIFT 30 61 #define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL 62 #define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1)) 63 /* L1 index Bit[29:21] */ 64 #define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL 65 #define PGTBL_L1_INDEX_SHIFT 21 66 #define PGTBL_L1_BLOCK_SHIFT 21 67 #define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL 68 #define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1)) 69 /* L0 index Bit[20:12] */ 70 #define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL 71 #define PGTBL_L0_INDEX_SHIFT 12 72 #define PGTBL_L0_BLOCK_SHIFT 12 73 #define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL 74 #define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1)) 75 76 #define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL 77 #define PGTBL_PTE_ADDR_SHIFT 10 78 #define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL 79 #define PGTBL_PTE_RSW_SHIFT 8 80 #define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL 81 #define PGTBL_PTE_DIRTY_SHIFT 7 82 #define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL 83 #define PGTBL_PTE_ACCESSED_SHIFT 6 84 #define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL 85 #define PGTBL_PTE_GLOBAL_SHIFT 5 86 #define PGTBL_PTE_USER_MASK 0x0000000000000010ULL 87 #define PGTBL_PTE_USER_SHIFT 4 88 #define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL 89 #define PGTBL_PTE_EXECUTE_SHIFT 3 90 #define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL 91 #define PGTBL_PTE_WRITE_SHIFT 2 92 #define PGTBL_PTE_READ_MASK 0x0000000000000002ULL 93 #define PGTBL_PTE_READ_SHIFT 1 94 #define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \ 95 PGTBL_PTE_DIRTY_MASK | \ 96 PGTBL_PTE_EXECUTE_MASK | \ 97 PGTBL_PTE_WRITE_MASK | \ 98 PGTBL_PTE_READ_MASK) 99 #define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL 100 #define PGTBL_PTE_VALID_SHIFT 0 101 102 #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE 103 #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT 104 105 /* SBI return error codes */ 106 #define SBI_SUCCESS 0 107 #define SBI_ERR_FAILURE -1 108 #define SBI_ERR_NOT_SUPPORTED -2 109 #define SBI_ERR_INVALID_PARAM -3 110 #define SBI_ERR_DENIED -4 111 #define SBI_ERR_INVALID_ADDRESS -5 112 #define SBI_ERR_ALREADY_AVAILABLE -6 113 #define SBI_ERR_ALREADY_STARTED -7 114 #define SBI_ERR_ALREADY_STOPPED -8 115 116 #define SBI_EXT_EXPERIMENTAL_START 0x08000000 117 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF 118 119 #define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END 120 #define KVM_RISCV_SELFTESTS_SBI_UCALL 0 121 #define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 122 123 enum sbi_ext_id { 124 SBI_EXT_BASE = 0x10, 125 SBI_EXT_STA = 0x535441, 126 }; 127 128 enum sbi_ext_base_fid { 129 SBI_EXT_BASE_PROBE_EXT = 3, 130 }; 131 132 struct sbiret { 133 long error; 134 long value; 135 }; 136 137 struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, 138 unsigned long arg1, unsigned long arg2, 139 unsigned long arg3, unsigned long arg4, 140 unsigned long arg5); 141 142 bool guest_sbi_probe_extension(int extid, long *out_val); 143 144 #endif /* SELFTEST_KVM_PROCESSOR_H */ 145