reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM

Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP.
SCU Manage resets for peripherals such as MIPI CSI. Currently, su

reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM

Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP.
SCU Manage resets for peripherals such as MIPI CSI. Currently, support two
reset sources: IMX_SC_R_CSI_0 and IMX_SC_R_CSI_1.

Signed-off-by: Frank Li <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: amlogic: move drivers to a dedicated directory

The meson reset driver will be split in two part, one implemeting the ops,
the other providing the platform driver support. This will be done to

reset: amlogic: move drivers to a dedicated directory

The meson reset driver will be split in two part, one implemeting the ops,
the other providing the platform driver support. This will be done to
facilitate the addition of the auxiliary bus support.

To avoid making a mess in drivers/reset/ while doing so, move the amlogic
reset drivers to a dedicated directory.

Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: eyeq: add platform driver

Add Mobileye EyeQ reset controller driver, for EyeQ5, EyeQ6L and EyeQ6H
SoCs. Instances belong to a shared register region called OLB and gets
spawned as auxiliary d

reset: eyeq: add platform driver

Add Mobileye EyeQ reset controller driver, for EyeQ5, EyeQ6L and EyeQ6H
SoCs. Instances belong to a shared register region called OLB and gets
spawned as auxiliary device to the platform driver for clock.

There is one OLB instance for EyeQ5 and EyeQ6L. There are seven OLB
instances on EyeQ6H; three have a reset controller embedded:
- West and east get handled by the same compatible.
- Acc (accelerator) is another one.

Each instance vary in the number and types of reset domains.
Instances with single domain expect a single cell, others two.

Signed-off-by: Théo Lebrun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: tegra-bpmp: allow building under COMPILE_TEST

The Tegra BPMP reset driver can be compiled without TEGRA_BPMP being
enabled. Allow it to be built under COMPILE_TEST.

Acked-by: Thierry Reding

reset: tegra-bpmp: allow building under COMPILE_TEST

The Tegra BPMP reset driver can be compiled without TEGRA_BPMP being
enabled. Allow it to be built under COMPILE_TEST.

Acked-by: Thierry Reding <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: zynqmp: allow building under COMPILE_TEST

The ZynqMP reset driver can be compiled without ARCH_ZYNQMP being
enabled. Allow it to be built under COMPILE_TEST.

Acked-by: Michal Simek <michal.s

reset: zynqmp: allow building under COMPILE_TEST

The ZynqMP reset driver can be compiled without ARCH_ZYNQMP being
enabled. Allow it to be built under COMPILE_TEST.

Acked-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: imx8mp-audiomix: Add AudioMix Block Control reset driver

Add support for the resets on i.MX8MP Audio Block Control module,
which includes the EARC PHY software reset and EARC controller
softw

reset: imx8mp-audiomix: Add AudioMix Block Control reset driver

Add support for the resets on i.MX8MP Audio Block Control module,
which includes the EARC PHY software reset and EARC controller
software reset. The reset controller is created using the auxiliary
device framework and set up in the clock driver.

Signed-off-by: Shengjiu Wang <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: sti: allow building under COMPILE_TEST

The STIH407 reset driver can be compiled without ARCH_STI being
enabled. Allow it to be built under COMPILE_TEST.

Reviewed-by: Patrice Chotard <patrice

reset: sti: allow building under COMPILE_TEST

The STIH407 reset driver can be compiled without ARCH_STI being
enabled. Allow it to be built under COMPILE_TEST.

Reviewed-by: Patrice Chotard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: gpio: Add GPIO-based reset controller

Add a simple driver to control GPIO-based resets using the reset
controller API for the cases when the GPIOs are shared and reset should
be coordinated.

reset: gpio: Add GPIO-based reset controller

Add a simple driver to control GPIO-based resets using the reset
controller API for the cases when the GPIOs are shared and reset should
be coordinated. The driver is expected to be used by reset core
framework for ad-hoc reset controllers.

Cc: Bartosz Golaszewski <[email protected]>
Cc: Chris Packham <[email protected]>
Cc: Sean Anderson <[email protected]>
Reviewed-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: Add Nuvoton ma35d1 reset driver support

This driver supports individual IP reset for the MA35D1. The reset
control registers are a subset of the system control registers.

Signed-off-by: Jack

reset: Add Nuvoton ma35d1 reset driver support

This driver supports individual IP reset for the MA35D1. The reset
control registers are a subset of the system control registers.

Signed-off-by: Jacky Huang <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Reviewed-by: Ilpo Järvinen <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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reset: oxnas: remove obsolete reset driver

Due to lack of maintainance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 a

reset: oxnas: remove obsolete reset driver

Due to lack of maintainance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 peripheral reset.

Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Daniel Golle <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Link: https://lore.kernel.org/r/20230331-topic-oxnas-upstream-remove-v1-17-5bd58fd1dd1f@linaro.org
Signed-off-by: Philipp Zabel <[email protected]>

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reset: Create subdirectory for StarFive drivers

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Reviewed-by: Philipp Zabel <

reset: Create subdirectory for StarFive drivers

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Reviewed-by: Philipp Zabel <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>

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reset: add polarfire soc reset support

Add support for the resets on Microchip's PolarFire SoC (MPFS).
Reset control is a single register, wedged in between registers for
clock control. To fit with

reset: add polarfire soc reset support

Add support for the resets on Microchip's PolarFire SoC (MPFS).
Reset control is a single register, wedged in between registers for
clock control. To fit with existed DT etc, the reset controller is
created using the aux device framework & set up in the clock driver.

Reviewed-by: Philipp Zabel <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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reset: tps380x: Add TPS380x device driver supprt

The TI TPS380x family [1] is a voltage supervisor with a dedicated
manual reset (mr) line input and a reset output. The chip(s) have a
build in reset

reset: tps380x: Add TPS380x device driver supprt

The TI TPS380x family [1] is a voltage supervisor with a dedicated
manual reset (mr) line input and a reset output. The chip(s) have a
build in reset delay, depending on the chip partnumber. This simple
driver addresses this so the cosumer don't need to care about it.

[1] https://www.ti.com/product/TPS3801

Signed-off-by: Marco Felsch <[email protected]>
[[email protected]: drop Todo comment about min/typ/max reset time]
Signed-off-by: Philipp Zabel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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reset: Add Sunplus SP7021 reset driver

Add reset driver for Sunplus SP7021 SoC.

Signed-off-by: Qin Jian <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Arnd

reset: Add Sunplus SP7021 reset driver

Add reset driver for Sunplus SP7021 SoC.

Signed-off-by: Qin Jian <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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reset: Add Delta TN48M CPLD reset controller

Delta TN48M CPLD exposes resets for the following:
* 88F7040 SoC
* 88F6820 SoC
* 98DX3265 switch MAC-s
* 88E1680 PHY-s
* 88E1512 PHY
* PoE PSE controller

reset: Add Delta TN48M CPLD reset controller

Delta TN48M CPLD exposes resets for the following:
* 88F7040 SoC
* 88F6820 SoC
* 98DX3265 switch MAC-s
* 88E1680 PHY-s
* 88E1512 PHY
* PoE PSE controller

Controller supports only self clearing resets.

Reviewed-by: Philipp Zabel <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Robert Marko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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reset: starfive-jh7100: Add StarFive JH7100 reset driver

Add a driver for the StarFive JH7100 reset controller.

Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Emil Renner B

reset: starfive-jh7100: Add StarFive JH7100 reset driver

Add a driver for the StarFive JH7100 reset controller.

Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

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reset: renesas: Add RZ/G2L usbphy control driver

Add support for RZ/G2L USBPHY Control driver. It mainly controls
reset and power down of the USB/PHY.

Signed-off-by: Biju Das <[email protected]

reset: renesas: Add RZ/G2L usbphy control driver

Add support for RZ/G2L USBPHY Control driver. It mainly controls
reset and power down of the USB/PHY.

Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Philipp Zabel <[email protected]>

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reset: stm32mp1: remove stm32mp1 reset

st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.

Signed-off-by: Gabriel Fernandez <[email protected]>
Link: https://lore.kernel.

reset: stm32mp1: remove stm32mp1 reset

st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver.

Signed-off-by: Gabriel Fernandez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Philipp Zabel <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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reset: mchp: sparx5: add switch reset driver

The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power

reset: mchp: sparx5: add switch reset driver

The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.

The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.

The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.

Signed-off-by: Steen Hegelund <[email protected]>
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>

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riscv: Add Canaan Kendryte K210 reset controller

Add a reset controller driver for the Canaan Kendryte K210 SoC. This
driver relies on its syscon compatible parent node (sysctl) for its
register map

riscv: Add Canaan Kendryte K210 reset controller

Add a reset controller driver for the Canaan Kendryte K210 SoC. This
driver relies on its syscon compatible parent node (sysctl) for its
register mapping. Default this driver compilation to y when the
SOC_CANAAN option is selected.

The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210
SOC RESET CONTROLLER DRIVER" with myself listed as maintainer for this
driver.

Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>

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reset: add BCM6345 reset controller driver

Add support for resetting blocks through the Linux reset controller
subsystem for BCM63xx SoCs.

Signed-off-by: Álvaro Fernández Rojas <[email protected]>

reset: add BCM6345 reset controller driver

Add support for resetting blocks through the Linux reset controller
subsystem for BCM63xx SoCs.

Signed-off-by: Álvaro Fernández Rojas <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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reset: Add Raspberry Pi 4 firmware reset controller

Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce

reset: Add Raspberry Pi 4 firmware reset controller

Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce a reset controller capable of interfacing with
RPi4's co-processor that models these firmware initialization routines as
reset lines.

Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Signed-off-by: Nicolas Saenz Julienne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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reset: Add Broadcom STB RESCAL reset controller

On BCM7216 there is a special purpose reset controller named RESCAL
(reset calibration) which is necessary for SATA and PCIe0/1 to operate
correctly.

reset: Add Broadcom STB RESCAL reset controller

On BCM7216 there is a special purpose reset controller named RESCAL
(reset calibration) which is necessary for SATA and PCIe0/1 to operate
correctly. This commit adds support for such a reset controller to be
available.

Signed-off-by: Jim Quinlan <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>

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reset: intel: Add system reset controller driver

Add driver for the reset controller present on Intel
Gateway SoCs for performing reset management of the
devices present on the SoC. Driver also regi

reset: intel: Add system reset controller driver

Add driver for the reset controller present on Intel
Gateway SoCs for performing reset management of the
devices present on the SoC. Driver also registers a
reset handler to peform the entire device reset.

Signed-off-by: Dilip Kota <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>

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reset: npcm: add NPCM reset controller driver

Add Nuvoton NPCM BMC reset controller driver.

Signed-off-by: Tomer Maimon <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>