PCI: amd-mdb: Add AMD MDB Root Port driver

Add support for AMD MDB (Multimedia DMA Bridge) IP core as Root Port.

The Versal2 devices include MDB Module. The integrated block for MDB
along with the

PCI: amd-mdb: Add AMD MDB Root Port driver

Add support for AMD MDB (Multimedia DMA Bridge) IP core as Root Port.

The Versal2 devices include MDB Module. The integrated block for MDB
along with the integrated bridge can function as PCIe Root Port
controller at Gen5 32-GT/s operation per lane.

Bridge supports error and INTx interrupts and are handled using platform
specific interrupt line in Versal2.

Signed-off-by: Thippeswamy Havalige <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[bhelgaas: only present on ARM64-based SoCs; squash Kconfig dependency on
ARM64 from Geert Uytterhoeven <[email protected]>:
https://lore.kernel.org/r/eaef1dea7edcf146aa377d5e5c5c85a76ff56bae.1742306383.git.geert+renesas@glider.be]
Signed-off-by: Bjorn Helgaas <[email protected]>
[kwilczynski: commit log, code comments and error messages clean-up,
drop redundant "depends on PCI" from Kconfig, expose the error code
as part of error messages where appropriatie, change "depends on"
expression to match existing style from other drivers]
Signed-off-by: Krzysztof Wilczyński <[email protected]>

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PCI: dwc: Add debugfs based Silicon Debug support for DWC

Add support to provide Silicon Debug interface to userspace.

This set of debug registers are part of the RAS DES feature present in
DesignW

PCI: dwc: Add debugfs based Silicon Debug support for DWC

Add support to provide Silicon Debug interface to userspace.

This set of debug registers are part of the RAS DES feature present in
DesignWare PCIe controllers.

Co-developed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Shradha Todi <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Fan Ni <[email protected]>
Tested-by: Hrishikesh Deleep <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[kwilczynski: commit log, tidy up Kconfig and drop "default y", tidy up
code comments, squashed patch that fixes a NULL pointer dereference when
debugfs is already unavailable during clean-up from
https://lore.kernel.org/linux-pci/[email protected],
refactor dwc_pcie_debugfs_init() to not return errors, squashed patch that
changes how lack of the RAS DES capability is handled from
https://lore.kernel.org/linux-pci/20250304151814.6xu7cbpwpqrvcad5@thinkpad]
Signed-off-by: Krzysztof Wilczyński <[email protected]>

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PCI: qcom: Add equalization settings for 16.0 GT/s

During high data transmission rates such as 16.0 GT/s, there is an
increased risk of signal loss due to poor channel quality and
interference. This

PCI: qcom: Add equalization settings for 16.0 GT/s

During high data transmission rates such as 16.0 GT/s, there is an
increased risk of signal loss due to poor channel quality and
interference. This can impact receiver's ability to capture signals
accurately.

Hence, as signal compensation is achieved through appropriate lane
equalization, apply lane equalization settings at both transmitter
and receiver which results in an increase in the PCIe signal strength.

While at it, modify the pcie-tegra194 driver to make use of the
common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h.

Link: https://lore.kernel.org/linux-pci/[email protected]
Tested-by: Johan Hovold <[email protected]>
Signed-off-by: Shashank Babu Chinta Venkata <[email protected]>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>

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PCI: dw-rockchip: Add endpoint mode support

The PCIe controller in rk3568 and rk3588 can operate in endpoint mode.

This endpoint mode support heavily leverages the existing code in
pcie-designware-

PCI: dw-rockchip: Add endpoint mode support

The PCIe controller in rk3568 and rk3588 can operate in endpoint mode.

This endpoint mode support heavily leverages the existing code in
pcie-designware-ep.c.

Add support for endpoint mode to the existing pcie-dw-rockchip glue
driver.

[kwilczynski: squash with patch adding the PCI_ENDPOINT dependency]
Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Niklas Cassel <[email protected]>
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>

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PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode

Add R-Car Gen4 PCIe controller support for host mode.

This controller is based on Synopsys DesignWare PCIe. However, this
partic

PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode

Add R-Car Gen4 PCIe controller support for host mode.

This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code like mode setting and retraining and
so on.

Link: https://lore.kernel.org/linux-pci/[email protected]
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Serge Semin <[email protected]>

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PCI: dwc: Add Baikal-T1 PCIe controller support

Baikal-T1 SoC is equipped with DWC PCIe v4.60a host controller. It can be
trained to work up to Gen.3 speed over up to x4 lanes. The host controller
i

PCI: dwc: Add Baikal-T1 PCIe controller support

Baikal-T1 SoC is equipped with DWC PCIe v4.60a host controller. It can be
trained to work up to Gen.3 speed over up to x4 lanes. The host controller
is attached to the DW PCIe 3.0 PCS via the PIPE-4 interface, which in its
turn is connected to the DWC 10G PHY. The whole system is supposed to be
fed up with four clock sources: DBI peripheral clock, AXI application
clocks and external PHY/core reference clock generating the 100MHz signal.
In addition to that the platform provide a way to reset each part of the
controller: sticky/non-sticky bits, host controller core, PIPE interface,
PCS/PHY and Hot/Power reset signal. The driver also provides a way to
handle the GPIO-based PERST# signal.

Note due to the Baikal-T1 MMIO peculiarity we have to implement the DBI
interface accessors which make sure the IO operations are dword-aligned.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Serge Semin <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>

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PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver

Add driver for Qualcomm PCIe Endpoint controller based on the DesignWare
core with added Qualcomm-specific wrapper around the core. The dri

PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver

Add driver for Qualcomm PCIe Endpoint controller based on the DesignWare
core with added Qualcomm-specific wrapper around the core. The driver
support is very basic such that it supports only enumeration, PCIe
read/write, and MSI. There is no ASPM and PM support for now but these will
be added later.

The driver is capable of using the PERST# and WAKE# side-band GPIOs for
operation and written on top of the DWC PCI framework.

[bhelgaas: wrap a few long lines]
Co-developed-by: Siddartha Mohanadoss <[email protected]>
[mani: restructured the driver and fixed several bugs for upstream]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Siddartha Mohanadoss <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

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PCI: rockchip-dwc: Add Rockchip RK356X host controller driver

Add a driver for the DesignWare-based PCIe controller found on
RK356X. The existing pcie-rockchip-host driver is only used for
the Rockc

PCI: rockchip-dwc: Add Rockchip RK356X host controller driver

Add a driver for the DesignWare-based PCIe controller found on
RK356X. The existing pcie-rockchip-host driver is only used for
the Rockchip-designed IP found on RK3399.

Link: https://lore.kernel.org/r/[email protected]
Tested-by: Peter Geis <[email protected]>
Signed-off-by: Simon Xue <[email protected]>
Signed-off-by: Shawn Lin <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

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PCI: visconti: Add Toshiba Visconti PCIe host controller driver

Add support for the PCIe RC controller on Toshiba Visconti ARM SoCs. This
PCIe controller is based on the Synopsys DesignWare PCIe co

PCI: visconti: Add Toshiba Visconti PCIe host controller driver

Add support for the PCIe RC controller on Toshiba Visconti ARM SoCs. This
PCIe controller is based on the Synopsys DesignWare PCIe core.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Yuji Ishikawa <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

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PCI: keembay: Add support for Intel Keem Bay

Add driver for Intel Keem Bay SoC PCIe controller. This controller
is based on DesignWare PCIe core.

In Root Complex mode, only internal reference clock

PCI: keembay: Add support for Intel Keem Bay

Add driver for Intel Keem Bay SoC PCIe controller. This controller
is based on DesignWare PCIe core.

In Root Complex mode, only internal reference clock is possible for
Keem Bay A0. For Keem Bay B0, external reference clock can be used
and will be the default configuration. Currently, keembay_pcie_of_data
structure has one member. It will be expanded later to handle this
difference.

Endpoint mode link initialization is handled by the boot firmware.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Wan Ahmad Zainie <[email protected]>
Signed-off-by: Srikanth Thokala <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Krzysztof Wilczyński <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Andy Shevchenko <[email protected]>

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PCI: tegra194: Fix MCFG quirk build regressions

7f100744749e ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata")
caused a few build regressions:

- 7f100744749e removed the Makefile rule for

PCI: tegra194: Fix MCFG quirk build regressions

7f100744749e ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata")
caused a few build regressions:

- 7f100744749e removed the Makefile rule for CONFIG_PCIE_TEGRA194, so
pcie-tegra.c can no longer be built as a module. Restore that rule.

- 7f100744749e added "#ifdef CONFIG_PCIE_TEGRA194" around the native
driver, but that's only set when the driver is built-in (for a module,
CONFIG_PCIE_TEGRA194_MODULE is defined).

The ACPI quirk is completely independent of the rest of the native
driver, so move the quirk to its own file and remove the #ifdef in the
native driver.

- 7f100744749e added symbols that are always defined but used only when
CONFIG_PCIEASPM, which causes warnings when CONFIG_PCIEASPM is not set:

drivers/pci/controller/dwc/pcie-tegra194.c:259:18: warning: ‘event_cntr_data_offset’ defined but not used [-Wunused-const-variable=]
drivers/pci/controller/dwc/pcie-tegra194.c:250:18: warning: ‘event_cntr_ctrl_offset’ defined but not used [-Wunused-const-variable=]
drivers/pci/controller/dwc/pcie-tegra194.c:243:27: warning: ‘pcie_gen_freq’ defined but not used [-Wunused-const-variable=]

Fixes: 7f100744749e ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jon Hunter <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>

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PCI: fu740: Add SiFive FU740 PCIe host controller driver

Add driver for the SiFive FU740 PCIe host controller.
This controller is based on the DesignWare PCIe core.

Co-developed-by: Henry Styles <h

PCI: fu740: Add SiFive FU740 PCIe host controller driver

Add driver for the SiFive FU740 PCIe host controller.
This controller is based on the DesignWare PCIe core.

Co-developed-by: Henry Styles <[email protected]>
Co-developed-by: Erik Danie <[email protected]>
Co-developed-by: Greentime Hu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Henry Styles <[email protected]>
Signed-off-by: Erik Danie <[email protected]>
Signed-off-by: Greentime Hu <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>

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PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata

The PCIe controller in Tegra194 SoC is not ECAM-compliant. With the
current hardware design, ECAM can be enabled only for one controller (the
C5

PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata

The PCIe controller in Tegra194 SoC is not ECAM-compliant. With the
current hardware design, ECAM can be enabled only for one controller (the
C5 controller) with bus numbers starting from 160 instead of 0. A different
approach is taken to avoid this abnormal way of enabling ECAM for just one
controller but to enable configuration space access for all the other
controllers. In this approach, ops are added through MCFG quirk mechanism
which access the configuration spaces by dynamically programming iATU
(internal AddressTranslation Unit) to generate respective configuration
accesses just like the way it is done in DesignWare core sub-system.

This issue is specific to Tegra194 and it would be fixed in the future
generations of Tegra SoCs.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>

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PCI: Avoid building empty drivers

There are harmless warnings when compile testing the kernel with
CONFIG_TRIM_UNUSED_KSYMS:

drivers/pci/controller/dwc/pcie-al.o: no symbols
drivers/pci/control

PCI: Avoid building empty drivers

There are harmless warnings when compile testing the kernel with
CONFIG_TRIM_UNUSED_KSYMS:

drivers/pci/controller/dwc/pcie-al.o: no symbols
drivers/pci/controller/pci-thunder-ecam.o: no symbols
drivers/pci/controller/pci-thunder-pem.o: no symbols

The problem here is that the host drivers get built even when the
configuration symbols are all disabled, as they pretend to not be drivers
but are silently enabled because of the promise that ACPI-based systems
need no drivers.

Add back the normal symbols to have these drivers built, and change the
logic to otherwise only build them when both CONFIG_PCI_QUIRKS and
CONFIG_ACPI are enabled.

As a side-effect, this enables compile-testing the drivers on other
architectures, which in turn needs the acpi_get_rc_resources() function to
be defined.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Robert Richter <[email protected]>

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PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver

Add driver for the Socionext UniPhier Pro5 SoC endpoint controller.
This controller is based on the DesignWare PCIe core.

PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver

Add driver for the Socionext UniPhier Pro5 SoC endpoint controller.
This controller is based on the DesignWare PCIe core.

And add "host" to existing controller descriontions for the host controller
in Kconfig.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kunihiko Hayashi <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

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PCI: dwc: intel: PCIe RC controller driver

Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare PCIe core.

Intel PCIe driver requires Upconfigure

PCI: dwc: intel: PCIe RC controller driver

Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare PCIe core.

Intel PCIe driver requires Upconfigure support, Fast Training
Sequence and link speed configurations. So adding the respective
helper functions in the PCIe DesignWare framework.
It also programs hardware autonomous speed during speed
configuration so defining it in pci_regs.h.

Also, mark Intel PCIe driver depends on MSI IRQ Domain
as Synopsys DesignWare framework depends on the
PCI_MSI_IRQ_DOMAIN.

Signed-off-by: Dilip Kota <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>

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PCI: tegra: Add Tegra194 PCIe support

Add support for Synopsys DesignWare core IP based PCIe host controller
present in the Tegra194 SoC.

Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-b

PCI: tegra: Add Tegra194 PCIe support

Add support for Synopsys DesignWare core IP based PCIe host controller
present in the Tegra194 SoC.

Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Thierry Reding <[email protected]>

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PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately

Add CONFIG_PCI_LAYERSCAPE_EP so that endpoint and host controller
drivers can be built separately.

Signed-off-by: Xiaowei Bao

PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately

Add CONFIG_PCI_LAYERSCAPE_EP so that endpoint and host controller
drivers can be built separately.

Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>

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PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

Add driver for Amazon's Annapurna Labs PCIe host controller. The
controller is based on DesignWare's IP.

The controller doesn't suppo

PCI: al: Add Amazon Annapurna Labs PCIe host controller driver

Add driver for Amazon's Annapurna Labs PCIe host controller. The
controller is based on DesignWare's IP.

The controller doesn't support accessing the Root Port's config space via
ECAM, so we obtain its base address via an AMZN0001 device.

Furthermore, the DesignWare PCIe controller doesn't filter out config
transactions sent to devices 1 and up on its bus, so they are filtered by
the driver.

All subordinate buses do support ECAM access.

Implementing specific PCI config access functions involves:
- Adding an init function to obtain the Root Port's base address from
an AMZN0001 device.
- Adding a new entry in the MCFG quirk array.

[bhelgaas: Note that there is no Kconfig option for this driver because it
is only intended for use with the generic ACPI host bridge driver. This
driver is only needed because the DesignWare IP doesn't completely support
ECAM access to the root bus.]

Link: https://lore.kernel.org/lkml/[email protected]
Co-developed-by: Vladimir Aerov <[email protected]>
Signed-off-by: Jonathan Chocron <[email protected]>
Signed-off-by: Vladimir Aerov <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: David Woodhouse <[email protected]>
Reviewed-by: Benjamin Herrenschmidt <[email protected]>
Acked-by: Lorenzo Pieralisi <[email protected]>

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PCI: layerscape: Add EP mode support

Add the PCIe EP mode support to the layerscape platform controller.

Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Lorenzo Pieralisi <lorenzo.p

PCI: layerscape: Add EP mode support

Add the PCIe EP mode support to the layerscape platform controller.

Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Minghuan Lian <[email protected]>
Reviewed-by: Zhiqiang Hou <[email protected]>
Reviewed-by: Kishon Vijay Abraham I <[email protected]>

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PCI: uniphier: Add UniPhier PCIe host controller support

This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the DesignWare PCIe core, and
this

PCI: uniphier: Add UniPhier PCIe host controller support

This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the DesignWare PCIe core, and
this driver supports Root Complex (host) mode.

Signed-off-by: Kunihiko Hayashi <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>

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PCI: amlogic: Add the Amlogic Meson PCIe controller driver

The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe cont

PCI: amlogic: Add the Amlogic Meson PCIe controller driver

The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.

Link: https://lore.kernel.org/linux-pci/[email protected]/
Signed-off-by: Yue Wang <[email protected]>
Signed-off-by: Hanjie Lin <[email protected]>
[[email protected]: updated coding/comment style]
Signed-off-by: Lorenzo Pieralisi <[email protected]>

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PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c

No functional change. Having two different files for keystone PCI driver
doesn't serve any purpose. Merge pci-keystone-dw.c and pci-keystone

PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c

No functional change. Having two different files for keystone PCI driver
doesn't serve any purpose. Merge pci-keystone-dw.c and pci-keystone.c
into a single pci-keystone.c file and remove pci-keystone.h.

Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>

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PCI: Collect all native drivers under drivers/pci/controller/

Native PCI drivers for root complex devices were originally all in
drivers/pci/host/. Some of these devices can also be operated in end

PCI: Collect all native drivers under drivers/pci/controller/

Native PCI drivers for root complex devices were originally all in
drivers/pci/host/. Some of these devices can also be operated in endpoint
mode. Drivers for endpoint mode didn't seem to fit in the "host"
directory, so we put both the root complex and endpoint drivers in
per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc.

These per-device directories contain trivial Kconfig and Makefiles and
clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and
collect all the device-specific drivers there.

No functional change intended.

Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Shawn Lin <[email protected]>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <[email protected]>

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