mailbox: add Samsung Exynos driver

The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16
flag bits for hardware interrupt generation and a shared register for
passing mailbox messa

mailbox: add Samsung Exynos driver

The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16
flag bits for hardware interrupt generation and a shared register for
passing mailbox messages. When the controller is used by the
ACPM interface the shared register is ignored and the mailbox controller
acts as a doorbell. The controller just raises the interrupt to APM
after the ACPM interface has written the message to SRAM.

Add support for the Samsung Exynos mailbox controller.

Signed-off-by: Tudor Ambarus <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: add Microchip IPC support

Add a mailbox controller driver for the Microchip Inter-processor
Communication (IPC), which is used to send and receive data between
processors.

The driver uses

mailbox: add Microchip IPC support

Add a mailbox controller driver for the Microchip Inter-processor
Communication (IPC), which is used to send and receive data between
processors.

The driver uses the RISC-V Supervisor Binary Interface (SBI) to
communicate with software running in machine mode (M-mode) to access
the IPC hardware block.

Additional details on the Microchip vendor extension and the IPC
function IDs described in the driver can be found in the following
documentation:

https://github.com/linux4microchip/microchip-sbi-ecall-extension

This SBI interface in this driver is compatible with the Mi-V Inter-hart
Communication (IHC) IP.

Transmitting and receiving data through the mailbox framework is done
through struct mchp_ipc_msg.

Signed-off-by: Valentina Fernandez <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: Introduce support for T-head TH1520 Mailbox driver

This driver was tested using the drm/imagination GPU driver. It was able
to successfully power on the GPU, by passing a command through ma

mailbox: Introduce support for T-head TH1520 Mailbox driver

This driver was tested using the drm/imagination GPU driver. It was able
to successfully power on the GPU, by passing a command through mailbox
from E910 core to E902 that's responsible for powering up the GPU. The
GPU driver was able to read the BVNC version from control registers,
which confirms it was successfully powered on.

[ 33.957467] powervr ffef400000.gpu: [drm] loaded firmware
powervr/rogue_36.52.104.182_v1.fw
[ 33.966008] powervr ffef400000.gpu: [drm] FW version v1.0 (build
6621747 OS)
[ 38.978542] powervr ffef400000.gpu: [drm] *ERROR* Firmware failed to
boot

Though the driver still fails to boot the firmware, the mailbox driver
works when used with the not-yet-upstreamed firmware AON driver. There
is ongoing work to get the BXM-4-64 supported with the drm/imagination
driver [1], though it's not completed yet.

This work is based on the driver from the vendor kernel [2].

Link: https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/2 [1]
Link: https://github.com/revyos/thead-kernel.git [2]

Signed-off-by: Michal Wilczynski <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: ti-msgmgr: Allow building under COMPILE_TEST

The TI message manager driver can be compiled without ARCH_KEYSTONE
nor ARCH_K3 enabled. Allow it to be built under COMPILE_TEST.

Signed-off-by

mailbox: ti-msgmgr: Allow building under COMPILE_TEST

The TI message manager driver can be compiled without ARCH_KEYSTONE
nor ARCH_K3 enabled. Allow it to be built under COMPILE_TEST.

Signed-off-by: Andrew Davis <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Reviewed-by: Nishanth Menon <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: mpfs: support new, syscon based, devicetree configuration

The two previous bindings for this hardware were incorrect, as the
control/status and interrupt register regions should have been d

mailbox: mpfs: support new, syscon based, devicetree configuration

The two previous bindings for this hardware were incorrect, as the
control/status and interrupt register regions should have been described
as syscons and dealt with via regmap in the driver. Add support for
accessing these registers using that method now, so that the hwmon
driver can be supported without using auxdev or hacks with io_remap().

Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox, remoteproc: omap2+: fix compile testing

Selecting CONFIG_OMAP2PLUS_MBOX while compile testing
causes a build failure:

WARNING: unmet direct dependencies detected for OMAP2PLUS_MBOX
Depen

mailbox, remoteproc: omap2+: fix compile testing

Selecting CONFIG_OMAP2PLUS_MBOX while compile testing
causes a build failure:

WARNING: unmet direct dependencies detected for OMAP2PLUS_MBOX
Depends on [n]: MAILBOX [=y] && (ARCH_OMAP2PLUS || ARCH_K3)
Selected by [m]:
- TI_K3_M4_REMOTEPROC [=m] && REMOTEPROC [=y] && (ARCH_K3 || COMPILE_TEST [=y])

Using 'select' to force-enable another subsystem is generally
a mistake and causes problems such as this one, so change the
three drivers that link against this driver to use 'depends on'
instead, and ensure the driver itself can be compile tested
regardless of the platform.

When compile-testing without CONFIG_TI_SCI_PROTOCOL=m, there
is a chance for a link failure, so add a careful dependency
on that.

arm-linux-gnueabi-ld: drivers/remoteproc/ti_k3_m4_remoteproc.o: in function `k3_m4_rproc_probe':
ti_k3_m4_remoteproc.c:(.text.k3_m4_rproc_probe+0x76): undefined reference to `devm_ti_sci_get_by_phandle'

Fixes: ebcf9008a895 ("remoteproc: k3-m4: Add a remoteproc driver for M4F subsystem")
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Mathieu Poirier <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
Reviewed-by: Martyn Welch <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: ARM_MHU_V3 should depend on ARM64

The ARM MHUv3 controller is only present on ARM64 SoCs. Hence add a
dependency on ARM64, to prevent asking the user about this driver when
configuring a k

mailbox: ARM_MHU_V3 should depend on ARM64

The ARM MHUv3 controller is only present on ARM64 SoCs. Hence add a
dependency on ARM64, to prevent asking the user about this driver when
configuring a kernel for a different architecture than ARM64.

Fixes: ca1a8680b134b5e6 ("mailbox: arm_mhuv3: Add driver")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Sudeep Holla <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: qcom-cpucp: fix 64BIT dependency

This newly added driver fails compile testing on 32-bit architectures
because it relies on 64-bit MMIO register access:

drivers/mailbox/qcom-cpucp-mbox.c:

mailbox: qcom-cpucp: fix 64BIT dependency

This newly added driver fails compile testing on 32-bit architectures
because it relies on 64-bit MMIO register access:

drivers/mailbox/qcom-cpucp-mbox.c: In function 'qcom_cpucp_mbox_irq_fn':
drivers/mailbox/qcom-cpucp-mbox.c:54:18: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Wimplicit-function-declaration]
54 | status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
| ^~~~~
| readb
drivers/mailbox/qcom-cpucp-mbox.c:65:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Wimplicit-function-declaration]
65 | writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
| ^~~~~~
| writeb

Change the Kconfig dependency to disallow that configuration as well.

Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller")
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: Add support for QTI CPUCP mailbox controller

Add support for CPUSS Control Processor (CPUCP) mailbox controller,
this driver enables communication between AP and CPUCP by acting as
a doorbe

mailbox: Add support for QTI CPUCP mailbox controller

Add support for CPUSS Control Processor (CPUCP) mailbox controller,
this driver enables communication between AP and CPUCP by acting as
a doorbell between them.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: arm_mhuv3: Add driver

Add support for ARM MHUv3 mailbox controller.

Support is limited to the MHUv3 Doorbell extension using only the PBX/MBX
combined interrupts.

Signed-off-by: Cristian

mailbox: arm_mhuv3: Add driver

Add support for ARM MHUv3 mailbox controller.

Support is limited to the MHUv3 Doorbell extension using only the PBX/MBX
combined interrupts.

Signed-off-by: Cristian Marussi <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: omap: Remove kernel FIFO message queuing

The kernel FIFO queue has a couple issues. The biggest issue is that
it causes extra latency in a path that can be used in real-time tasks,
such as

mailbox: omap: Remove kernel FIFO message queuing

The kernel FIFO queue has a couple issues. The biggest issue is that
it causes extra latency in a path that can be used in real-time tasks,
such as communication with real-time remote processors.

The whole FIFO idea itself looks to be a leftover from before the
unified mailbox framework. The current mailbox framework expects
mbox_chan_received_data() to be called with data immediately as it
arrives. Remove the FIFO and pass the messages to the mailbox
framework directly as part of a threaded IRQ handler.

Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: apple: Delete driver

This driver is now orphaned and superseded by
drivers/soc/apple/mailbox.c.

Acked-by: Eric Curtin <[email protected]>
Acked-by: Neal Gompa <[email protected]>
Acked-by: A

mailbox: apple: Delete driver

This driver is now orphaned and superseded by
drivers/soc/apple/mailbox.c.

Acked-by: Eric Curtin <[email protected]>
Acked-by: Neal Gompa <[email protected]>
Acked-by: Alyssa Rosenzweig <[email protected]>
Signed-off-by: Hector Martin <[email protected]>

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mailbox: mpfs: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE

As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert t

mailbox: mpfs: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE

As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert the Microchip FPGA
mailbox driver to use the new symbol.

Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: zynq: make modular

This driver has a MODULE_LICENSE but is not tristate so cannot be
built as a module, unlike all its peers: make it modular to match.

Signed-off-by: Nick Alcock <nick.alc

mailbox: zynq: make modular

This driver has a MODULE_LICENSE but is not tristate so cannot be
built as a module, unlike all its peers: make it modular to match.

Signed-off-by: Nick Alcock <[email protected]>
Suggested-by: Michal Simek <[email protected]>
Cc: Luis Chamberlain <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Hitomi Hasegawa <[email protected]>
Cc: Jassi Brar <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: [email protected]
Signed-off-by: Luis Chamberlain <[email protected]>

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mailbox: config: ti-msgmgr: Default set to ARCH_K3 for TI msg manager

Defaulting the build to ARCH_K3 for the TI message manager driver.

Signed-off-by: Nicolas Frayer <[email protected]>
Signed-

mailbox: config: ti-msgmgr: Default set to ARCH_K3 for TI msg manager

Defaulting the build to ARCH_K3 for the TI message manager driver.

Signed-off-by: Nicolas Frayer <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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genirq: Get rid of GENERIC_MSI_IRQ_DOMAIN

Adjust to reality and remove another layer of pointless Kconfig
indirection. CONFIG_GENERIC_MSI_IRQ is good enough to serve
all purposes.

Signed-off-by: Th

genirq: Get rid of GENERIC_MSI_IRQ_DOMAIN

Adjust to reality and remove another layer of pointless Kconfig
indirection. CONFIG_GENERIC_MSI_IRQ is good enough to serve
all purposes.

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Jason Gunthorpe <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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mailbox: mediatek: add support for adsp mailbox controller

This patch is to for MediaTek ADSP IPC mailbox controller driver
It is used to send short messages between processors with adsp

Signed-off

mailbox: mediatek: add support for adsp mailbox controller

This patch is to for MediaTek ADSP IPC mailbox controller driver
It is used to send short messages between processors with adsp

Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: Tzung-Bi Shih <[email protected]>
Reviewed-by: YC Hung <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: apple: Add driver for Apple mailboxes

Apple SoCs such as the M1 come with various co-processors. Mailboxes
are used to communicate with those. This driver adds support for
two variants of t

mailbox: apple: Add driver for Apple mailboxes

Apple SoCs such as the M1 come with various co-processors. Mailboxes
are used to communicate with those. This driver adds support for
two variants of those mailboxes.

Signed-off-by: Sven Peter <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module

This patch enables the qcom_ipcc driver to be loaded as a
module. IPCC is fairly core to system, so as such it should
never be unloaded. It r

mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module

This patch enables the qcom_ipcc driver to be loaded as a
module. IPCC is fairly core to system, so as such it should
never be unloaded. It registers as a mailbox + irq controller
and the irq controller drivers in kernel are not supposed to
be unloaded as they don't have the visibility over the clients
consuming the irqs. Hence adding supress_bind_attrs to disable
bind/unbind via sysfs.

Signed-off-by: Amit Pundir <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mbox: add polarfire soc system controller mailbox

This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <c

mbox: add polarfire soc system controller mailbox

This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: fix various typos in comments

Fix trivial typos in mailbox driver comments.

s/Intergrated/Integrated/
s/extenstion/extension/
s/atleast/at least/
s/commnunication/communication/
s/assgined

mailbox: fix various typos in comments

Fix trivial typos in mailbox driver comments.

s/Intergrated/Integrated/
s/extenstion/extension/
s/atleast/at least/
s/commnunication/communication/
s/assgined/assigned/
s/commnunication/communication/
s/recevied/received/
s/succeded/succeeded/
s/implmentation/implementation/
s/definiation/definition/
s/traget/target/
s/wont/won't/

Cc: [email protected]
Signed-off-by: Tom Saeger <[email protected]>
Reviewed-by: Randy Dunlap <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: arm_mhuv2: Add driver

This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox
controller.

This is based on the accepted DT bindings of the controller and supports
combination of

mailbox: arm_mhuv2: Add driver

This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox
controller.

This is based on the accepted DT bindings of the controller and supports
combination of both transport protocols, i.e. doorbell and data-transfer.

Transmitting and receiving data through the mailbox framework is done
through struct arm_mhuv2_mbox_msg.

Based on the initial work done by Morten Borup Petersen from ARM.

Co-developed-by: Tushar Khandelwal <[email protected]>
Signed-off-by: Tushar Khandelwal <[email protected]>
Tested-by: Usama Arif <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: stm32-ipcc: add COMPILE_TEST dependency

This allows compiling the driver on architectures where the hardware is not
available. Most other mailbox drivers support this as well.

Signed-off-b

mailbox: stm32-ipcc: add COMPILE_TEST dependency

This allows compiling the driver on architectures where the hardware is not
available. Most other mailbox drivers support this as well.

Signed-off-by: Martin Kaiser <[email protected]>
Reviewed-by: Fabien Dessenne <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: Add support for Qualcomm IPCC

Add support for the Inter-Processor Communication Controller (IPCC)
block from Qualcomm that coordinates the interrupts (inbound & outbound)
for Multiprocessor

mailbox: Add support for Qualcomm IPCC

Add support for the Inter-Processor Communication Controller (IPCC)
block from Qualcomm that coordinates the interrupts (inbound & outbound)
for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1
(COMPUTE-L1) protocols for the Application Processor Subsystem (APSS).

This driver is modeled as an irqchip+mailbox driver. The irqchip part
helps in receiving the interrupts from the IPCC clients such as modems,
DSPs, PCI-E etc... and forwards them to respective entities in APSS.

On the other hand, the mailbox part is used to send interrupts to the IPCC
clients from the entities of APSS.

Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Raghavendra Rao Ananta <[email protected]>
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
[mani: moved to mailbox, added static mbox channels and cleanups]
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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mailbox: sprd: Add Spreadtrum mailbox driver

The Spreadtrum mailbox controller supports 8 channels to communicate
with MCUs, and it contains 2 different parts: inbox and outbox, which
are used to se

mailbox: sprd: Add Spreadtrum mailbox driver

The Spreadtrum mailbox controller supports 8 channels to communicate
with MCUs, and it contains 2 different parts: inbox and outbox, which
are used to send and receive messages by IRQ mode.

Signed-off-by: Baolin Wang <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

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