drm/amd/display: Adjust reg field for DSC wait for disconnect[WHY]DSC was waiting for the wrong field to disconnect cleanly.[HOW]Changed field the DSC disconnect was waiting on.Reviewed-by: W
drm/amd/display: Adjust reg field for DSC wait for disconnect[WHY]DSC was waiting for the wrong field to disconnect cleanly.[HOW]Changed field the DSC disconnect was waiting on.Reviewed-by: Wenjing Liu <[email protected]>Cc: Mario Limonciello <[email protected]>Cc: Alex Deucher <[email protected]>Cc: [email protected]Signed-off-by: Alex Hung <[email protected]>Signed-off-by: Ryan Seto <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
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drm/amd/display: Reset DSC memory status[WHY]When system exits idle state followed by enabling the display,DSC memory may still be forced in a deep sleep or shutdown state.Intermittent DSC corr
drm/amd/display: Reset DSC memory status[WHY]When system exits idle state followed by enabling the display,DSC memory may still be forced in a deep sleep or shutdown state.Intermittent DSC corruption is seen when display is visible.[HOW]When DSC is enabled, reset dsc memory to force and disable status.Reviewed-by: Nicholas Kazlauskas <[email protected]>Cc: Mario Limonciello <[email protected]>Cc: Alex Deucher <[email protected]>Cc: [email protected]Signed-off-by: Alex Hung <[email protected]>Signed-off-by: Duncan Ma <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: reset DSC clock in post unlock update[why]Switching between DSC clock or disable DSC block are not double buffered update.Corruption is observed if these updates happen before DS
drm/amd/display: reset DSC clock in post unlock update[why]Switching between DSC clock or disable DSC block are not double buffered update.Corruption is observed if these updates happen before DSC double buffereddisconnection.[how]Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffereddisconnection and all mpccs are disconnected before reset DSC clock.Reviewed-by: Samson Tam <[email protected]>Acked-by: Tom Chung <[email protected]>Signed-off-by: Wenjing Liu <[email protected]>Tested-by: Daniel Wheeler <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add some DCN401 reg name to macro definitionsUpdate macros to cover DCN 4.0.1.Signed-off-by: Aurabindo Pillai <[email protected]>Acked-by: Rodrigo Siqueira <rodrigo.sique
drm/amd/display: Add some DCN401 reg name to macro definitionsUpdate macros to cover DCN 4.0.1.Signed-off-by: Aurabindo Pillai <[email protected]>Acked-by: Rodrigo Siqueira <[email protected]>Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Refactor DSC into component folder[why]To refactor DSC and make DSC files unit testable.[how]moved the dcnxx_dsc.c and .h filesinto corresponding dcn folders insidethe dsc
drm/amd/display: Refactor DSC into component folder[why]To refactor DSC and make DSC files unit testable.[how]moved the dcnxx_dsc.c and .h filesinto corresponding dcn folders insidethe dsc and cleared the linkage errors.Reviewed-by: Wenjing Liu <[email protected]>Acked-by: Hamza Mahfooz <[email protected]>Signed-off-by: Bhuvana Chandra Pinninti <[email protected]>Signed-off-by: Alex Deucher <[email protected]>