1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 6 #include "dml2_internal_types.h" 7 #include "dml_top.h" 8 #include "dml2_core_dcn4_calcs.h" 9 #include "dml2_internal_shared_types.h" 10 #include "dml21_utils.h" 11 #include "dml21_translation_helper.h" 12 #include "dml2_dc_resource_mgmt.h" 13 14 static bool dml21_allocate_memory(struct dml2_context **dml_ctx) 15 { 16 *dml_ctx = (struct dml2_context *)kzalloc(sizeof(struct dml2_context), GFP_KERNEL); 17 if (!(*dml_ctx)) 18 return false; 19 20 (*dml_ctx)->v21.dml_init.dml2_instance = (struct dml2_instance *)kzalloc(sizeof(struct dml2_instance), GFP_KERNEL); 21 if (!((*dml_ctx)->v21.dml_init.dml2_instance)) 22 return false; 23 24 (*dml_ctx)->v21.mode_support.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; 25 (*dml_ctx)->v21.mode_programming.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance; 26 27 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; 28 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; 29 30 (*dml_ctx)->v21.mode_programming.programming = (struct dml2_display_cfg_programming *)kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL); 31 if (!((*dml_ctx)->v21.mode_programming.programming)) 32 return false; 33 34 return true; 35 } 36 37 static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) 38 { 39 bool disable_fams2; 40 struct dml2_pmo_options *pmo_options = &dml_ctx->v21.dml_init.options.pmo_options; 41 42 /* ODM options */ 43 pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm; 44 pmo_options->disable_dyn_odm_for_multi_stream = true; 45 pmo_options->disable_dyn_odm_for_stream_with_svp = true; 46 47 /* UCLK P-State options */ 48 if (in_dc->debug.dml21_force_pstate_method) { 49 dml_ctx->config.pmo.force_pstate_method_enable = true; 50 for (int i = 0; i < MAX_PIPES; i++) 51 dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; 52 } else { 53 dml_ctx->config.pmo.force_pstate_method_enable = false; 54 } 55 56 pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1); 57 58 /* NOTE: DRR and SubVP Require FAMS2 */ 59 disable_fams2 = !in_dc->debug.fams2_config.bits.enable; 60 pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) || 61 in_dc->debug.force_disable_subvp || 62 disable_fams2; 63 pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) || 64 disable_fams2; 65 pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) || 66 disable_fams2; 67 pmo_options->disable_fams2 = disable_fams2; 68 69 pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming; 70 } 71 72 static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 73 { 74 switch (in_dc->ctx->dce_version) { 75 case DCN_VERSION_4_01: 76 case DCN_VERSION_3_2: // TODO : Temporary for N-1 validation. Remove this after N-1 validation phase is complete. 77 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp; 78 break; 79 default: 80 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_invalid; 81 } 82 83 (*dml_ctx)->architecture = dml2_architecture_21; 84 85 /* Store configuration options */ 86 (*dml_ctx)->config = *config; 87 88 /*Initialize SOCBB and DCNIP params */ 89 dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc); 90 dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc); 91 dml21_apply_soc_bb_overrides(&(*dml_ctx)->v21.dml_init, config, in_dc); 92 93 /* apply debug overrides */ 94 dml21_apply_debug_options(in_dc, *dml_ctx, config); 95 96 /*Initialize DML21 instance */ 97 dml2_initialize_instance(&(*dml_ctx)->v21.dml_init); 98 } 99 100 bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 101 { 102 /* Allocate memory for initializing DML21 instance */ 103 if (!dml21_allocate_memory(dml_ctx)) 104 return false; 105 106 dml21_init(in_dc, dml_ctx, config); 107 108 return true; 109 } 110 111 void dml21_destroy(struct dml2_context *dml2) 112 { 113 kfree(dml2->v21.dml_init.dml2_instance); 114 kfree(dml2->v21.mode_programming.programming); 115 } 116 117 static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, 118 struct dml2_context *in_ctx, unsigned int pipe_cnt) 119 { 120 unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; 121 struct dml2_per_plane_programming *pln_prog = NULL; 122 struct dml2_per_stream_programming *stream_prog = NULL; 123 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 124 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 125 int num_pipes; 126 127 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 128 129 /* copy global DCHUBBUB arbiter registers */ 130 memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); 131 132 /* legacy only */ 133 context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; 134 135 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; 136 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; 137 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; 138 139 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { 140 pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 141 142 if (!pln_prog->plane_descriptor) 143 continue; 144 145 stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; 146 num_dpps_required = pln_prog->num_dpps_required; 147 148 if (num_dpps_required == 0) { 149 continue; 150 } 151 num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 152 153 if (num_pipes <= 0) 154 continue; 155 156 /* program each pipe */ 157 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 158 dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); 159 160 if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { 161 dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); 162 } 163 } 164 } 165 166 /* assign global clocks */ 167 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; 168 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; 169 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { 170 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = 171 in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; 172 } else { 173 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; 174 } 175 176 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { 177 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 178 in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; 179 } else { 180 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; 181 } 182 183 /* get global mall allocation */ 184 if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { 185 context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); 186 } else { 187 context->bw_ctx.bw.dcn.clk.num_ways = 0; 188 } 189 } 190 191 static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 192 { 193 bool result = false; 194 struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; 195 196 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); 197 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 198 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); 199 200 if (!context || context->stream_count == 0) 201 return true; 202 203 /* scrub phantom's from current dc_state */ 204 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); 205 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 206 207 /* Populate stream, plane mappings and other fields in display config. */ 208 result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 209 if (!result) 210 return false; 211 212 result = dml2_build_mode_programming(mode_programming); 213 if (!result) 214 return false; 215 216 /* Check and map HW resources */ 217 if (result && !dml_ctx->config.skip_hw_state_mapping) { 218 dml21_map_hw_resources(dml_ctx); 219 dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); 220 /* if subvp phantoms are present, expand them into dc context */ 221 dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); 222 } 223 224 /* Copy DML CLK, WM and REG outputs to bandwidth context */ 225 if (result && !dml_ctx->config.skip_hw_state_mapping) { 226 dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); 227 dml21_copy_clocks_to_dc_state(dml_ctx, context); 228 dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); 229 if (in_dc->ctx->dce_version == DCN_VERSION_3_2) { 230 dml21_extract_legacy_watermark_set(in_dc, &context->bw_ctx.bw.dcn.watermarks.a, DML2_DCHUB_WATERMARK_SET_A, dml_ctx); 231 dml21_extract_legacy_watermark_set(in_dc, &context->bw_ctx.bw.dcn.watermarks.b, DML2_DCHUB_WATERMARK_SET_A, dml_ctx); 232 dml21_extract_legacy_watermark_set(in_dc, &context->bw_ctx.bw.dcn.watermarks.c, DML2_DCHUB_WATERMARK_SET_A, dml_ctx); 233 dml21_extract_legacy_watermark_set(in_dc, &context->bw_ctx.bw.dcn.watermarks.d, DML2_DCHUB_WATERMARK_SET_A, dml_ctx); 234 } 235 236 dml21_build_fams2_programming(in_dc, context, dml_ctx); 237 } 238 239 return true; 240 } 241 242 static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 243 { 244 bool is_supported = false; 245 struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; 246 struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; 247 248 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); 249 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); 250 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); 251 252 if (!context || context->stream_count == 0) 253 return true; 254 255 /* Scrub phantom's from current dc_state */ 256 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); 257 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); 258 259 mode_support->dml2_instance = dml_init->dml2_instance; 260 dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); 261 dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; 262 is_supported = dml2_check_mode_supported(mode_support); 263 if (!is_supported) 264 return false; 265 266 return true; 267 } 268 269 bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, bool fast_validate) 270 { 271 bool out = false; 272 273 /* Use dml_validate_only for fast_validate path */ 274 if (fast_validate) { 275 out = dml21_check_mode_support(in_dc, context, dml_ctx); 276 } else 277 out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); 278 return out; 279 } 280 281 void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) 282 { 283 unsigned int num_pipes, dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; 284 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 285 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 286 287 struct dml2_per_plane_programming *pln_prog = NULL; 288 struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; 289 struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; 290 291 if (context->stream_count == 0) { 292 return; 293 } 294 295 memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); 296 l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; 297 298 /* phantom's start after main planes */ 299 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; 300 301 /* Build mcache programming parameters per plane per pipe */ 302 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { 303 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 304 305 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; 306 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 307 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 308 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; 309 mcache_config->num_pipes = pln_prog->num_dpps_required; 310 l->build_mcache_programming_params.num_configurations++; 311 312 if (pln_prog->num_dpps_required == 0) { 313 continue; 314 } 315 316 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 317 318 if (num_pipes <= 0 || 319 dc_main_pipes[0]->stream == NULL || 320 dc_main_pipes[0]->plane_state == NULL) 321 continue; 322 323 /* get config for each pipe */ 324 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 325 ASSERT(dc_main_pipes[dc_pipe_index]); 326 dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); 327 } 328 329 /* get config for each phantom pipe */ 330 if (pln_prog->phantom_plane.valid && 331 dc_phantom_pipes[0] && 332 dc_main_pipes[0]->stream && 333 dc_phantom_pipes[0]->plane_state) { 334 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; 335 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 336 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 337 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; 338 mcache_config->num_pipes = pln_prog->num_dpps_required; 339 l->build_mcache_programming_params.num_configurations++; 340 341 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 342 ASSERT(dc_phantom_pipes[dc_pipe_index]); 343 dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); 344 } 345 346 /* increment phantom index */ 347 dml_phantom_prog_idx++; 348 } 349 } 350 351 /* Call to generate mcache programming per plane per pipe for the given display configuration */ 352 dml2_build_mcache_programming(&l->build_mcache_programming_params); 353 354 /* get per plane per pipe mcache programming */ 355 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { 356 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; 357 358 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); 359 360 if (num_pipes <= 0 || 361 dc_main_pipes[0]->stream == NULL || 362 dc_main_pipes[0]->plane_state == NULL) 363 continue; 364 365 /* get config for each pipe */ 366 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 367 ASSERT(dc_main_pipes[dc_pipe_index]); 368 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { 369 memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, 370 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], 371 sizeof(struct dml2_hubp_pipe_mcache_regs)); 372 } 373 } 374 375 /* get config for each phantom pipe */ 376 if (pln_prog->phantom_plane.valid && 377 dc_phantom_pipes[0] && 378 dc_main_pipes[0]->stream && 379 dc_phantom_pipes[0]->plane_state) { 380 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { 381 ASSERT(dc_phantom_pipes[dc_pipe_index]); 382 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { 383 memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, 384 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], 385 sizeof(struct dml2_hubp_pipe_mcache_regs)); 386 } 387 } 388 /* increment phantom index */ 389 dml_phantom_prog_idx++; 390 } 391 } 392 } 393 394 void dml21_copy(struct dml2_context *dst_dml_ctx, 395 struct dml2_context *src_dml_ctx) 396 { 397 /* Preserve references to internals */ 398 struct dml2_instance *dst_dml2_instance = dst_dml_ctx->v21.dml_init.dml2_instance; 399 struct dml2_display_cfg_programming *dst_dml2_programming = dst_dml_ctx->v21.mode_programming.programming; 400 401 /* Copy context */ 402 memcpy(dst_dml_ctx, src_dml_ctx, sizeof(struct dml2_context)); 403 404 /* Copy Internals */ 405 memcpy(dst_dml2_instance, src_dml_ctx->v21.dml_init.dml2_instance, sizeof(struct dml2_instance)); 406 memcpy(dst_dml2_programming, src_dml_ctx->v21.mode_programming.programming, sizeof(struct dml2_display_cfg_programming)); 407 408 /* Restore references to internals */ 409 dst_dml_ctx->v21.dml_init.dml2_instance = dst_dml2_instance; 410 411 dst_dml_ctx->v21.mode_support.dml2_instance = dst_dml2_instance; 412 dst_dml_ctx->v21.mode_programming.dml2_instance = dst_dml2_instance; 413 414 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config; 415 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config; 416 417 dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming; 418 419 /* need to initialize copied instance for internal references to be correct */ 420 dml2_initialize_instance(&dst_dml_ctx->v21.dml_init); 421 } 422 423 bool dml21_create_copy(struct dml2_context **dst_dml_ctx, 424 struct dml2_context *src_dml_ctx) 425 { 426 /* Allocate memory for initializing DML21 instance */ 427 if (!dml21_allocate_memory(dst_dml_ctx)) 428 return false; 429 430 dml21_copy(*dst_dml_ctx, src_dml_ctx); 431 432 return true; 433 } 434 435 void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) 436 { 437 dml21_init(in_dc, dml_ctx, config); 438 } 439 440