fpga: xilinx-selectmap: add new driver

Xilinx 7 series FPGA can be programmed using a parallel port named
the SelectMAP interface in the datasheet. This interface is compatible
with the i.MX6 EIM bu

fpga: xilinx-selectmap: add new driver

Xilinx 7 series FPGA can be programmed using a parallel port named
the SelectMAP interface in the datasheet. This interface is compatible
with the i.MX6 EIM bus controller but other types of external memory
mapped parallel bus might work.

xilinx-selectmap currently only supports the x8 mode where data is loaded
at one byte per rising edge of the clock, with the MSb of each byte
presented to the D0 pin.

Signed-off-by: Charles Perry <[email protected]>
[[email protected]: replace data type of i from u32 to size_t]
Acked-by: Xu Yilun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: xilinx-spi: extract a common driver core

Factor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE)
protocol in xilinx-core so that it can be reused for another driver.
This commit doe

fpga: xilinx-spi: extract a common driver core

Factor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE)
protocol in xilinx-core so that it can be reused for another driver.
This commit does not change anything functionally to xilinx-spi.

xilinx-core expects drivers to provide a write(const char* buf,
size_t count) function that performs the actual write to the device,
as well as a struct device* for resource management.

Signed-off-by: Charles Perry <[email protected]>
Acked-by: Xu Yilun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: add configuration for the FPGA KUnit test suites.

Add configuration for the KUnit test suites for the core components
of the FPGA subsystem.

Signed-off-by: Marco Pagani <[email protected]>

fpga: add configuration for the FPGA KUnit test suites.

Add configuration for the KUnit test suites for the core components
of the FPGA subsystem.

Signed-off-by: Marco Pagani <[email protected]>
Acked-by: Xu Yilun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager

Add support to the FPGA manager for programming Lattice ECP5 FPGA over
slave SPI sysCONFIG interface.

sysCONFIG interface core functi

fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager

Add support to the FPGA manager for programming Lattice ECP5 FPGA over
slave SPI sysCONFIG interface.

sysCONFIG interface core functionality is separate from both ECP5 and
SPI specifics, so support for other FPGAs with different port types can
be added in the future.

Signed-off-by: Ivan Bornyakov <[email protected]>
Acked-by: Xu Yilun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: remove redundant blank line after kmemdup]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: microchip-spi: add Microchip MPF FPGA manager

Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Signed-off

fpga: microchip-spi: add Microchip MPF FPGA manager

Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Signed-off-by: Ivan Bornyakov <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Tested-by: Conor Dooley <[email protected]>
Acked-by: Xu Yilun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: m10bmc-sec: create max10 bmc secure update

Create a sub-driver for the FPGA Card BMC in order to support secure
updates. This patch creates the Max10 BMC Secure Update driver and
provides sys

fpga: m10bmc-sec: create max10 bmc secure update

Create a sub-driver for the FPGA Card BMC in order to support secure
updates. This patch creates the Max10 BMC Secure Update driver and
provides sysfs files for displaying the root entry hashes (REH) for the
FPGA static region (SR), the FPGA Partial Reconfiguration (PR) region,
and the card BMC.

The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmware
and FPGA images are authenticated using ECDSA before loading and executing
on the card. Code Signing Keys (CSK) are used to sign images. CSKs are
signed by a root key. The root entry hash is created from the root public
key.

The RoT provides authentication by storing an REH bitstream to a write-once
location. Image signatures are verified against the hash.

Reviewed-by: Tom Rix <[email protected]>
Tested-by: Tianfei Zhang <[email protected]>
Signed-off-by: Russ Weight <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: Use tab instead of space indentation

In FPGA Makefile has both space and tab indentation, to
make them align use tab instead of space indentation.

Signed-off-by: Nava kishore Manne <nava.mann

fpga: Use tab instead of space indentation

In FPGA Makefile has both space and tab indentation, to
make them align use tab instead of space indentation.

Signed-off-by: Nava kishore Manne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xu Yilun <[email protected]>

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fpga: versal-fpga: Add versal fpga manager driver

Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since dr

fpga: versal-fpga: Add versal fpga manager driver

Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.

Reviewed-by: Moritz Fischer <[email protected]>
Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
Signed-off-by: Nava kishore Manne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: add support for N3000 Nios private feature

This patch adds support for the Nios handshake private feature on Intel
PAC (Programmable Acceleration Card) N3000.

The Nios is the embedded pr

fpga: dfl: add support for N3000 Nios private feature

This patch adds support for the Nios handshake private feature on Intel
PAC (Programmable Acceleration Card) N3000.

The Nios is the embedded processor on the FPGA card. This private feature
provides a handshake interface to FPGA Nios firmware, which receives
retimer configuration command from host and executes via an internal SPI
master (spi-altera). When Nios finishes the configuration, host takes over
the ownership of the SPI master to control an Intel MAX10 BMC (Board
Management Controller) Chip on the SPI bus.

For Nios firmware handshake part, this driver requests the retimer
configuration for Nios firmware on probe, and adds some sysfs nodes for
user to query the onboard retimer's working mode and Nios firmware
version.

For SPI part, this driver adds a spi-altera platform device as well as
the MAX10 BMC spi slave info. A spi-altera driver will be matched to
handle the following SPI work.

[[email protected]: Fixed up ABI doc kernel release]

Reviewed-by: Tom Rix <[email protected]>
Signed-off-by: Xu Yilun <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Signed-off-by: Matthew Gerlach <[email protected]>
Signed-off-by: Russ Weight <[email protected]>
Signed-off-by: YueHaibing <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: fme: add performance reporting support

This patch adds support for performance reporting private feature
for FPGA Management Engine (FME). Now it supports several different
performance co

fpga: dfl: fme: add performance reporting support

This patch adds support for performance reporting private feature
for FPGA Management Engine (FME). Now it supports several different
performance counters, including 'basic', 'cache', 'fabric', 'vtd'
and 'vtd_sip'. It allows user to use standard linux tools to access
these performance counters.

e.g. List all events by "perf list"

perf list | grep fme

dfl_fme0/cache_read_hit/ [Kernel PMU event]
dfl_fme0/cache_read_miss/ [Kernel PMU event]
...

dfl_fme0/fab_mmio_read/ [Kernel PMU event]
dfl_fme0/fab_mmio_write/ [Kernel PMU event]
...

dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event]
dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event]
...

dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event]
dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event]
...

dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event]
dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event]
...

dfl_fme0/clock [Kernel PMU event]
...

e.g. check increased counter value after run one application using
"perf stat" command.

perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test

Performance counter stats for './test':

1 dfl_fme0/fab_mmio_read/
2 dfl_fme0/fab_mmio_write/

1.009496520 seconds time elapsed

Please note that fabric counters support both fab_* and fab_port_*, but
actually they are sharing one set of performance counters in hardware.
If user wants to monitor overall data events on fab_* then fab_port_*
can't be supported at the same time, see example below:

perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/

Performance counter stats for 'system wide':

0 dfl_fme0/fab_mmio_read/
<not supported> dfl_fme0/fab_port_mmio_write,portid=0/

2.141064085 seconds time elapsed

Signed-off-by: Luwei Kang <[email protected]>
Signed-off-by: Xu Yilun <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: fme: add global error reporting support

This patch adds support for global error reporting for FPGA
Management Engine (FME), it introduces sysfs interfaces to
report different error detec

fpga: dfl: fme: add global error reporting support

This patch adds support for global error reporting for FPGA
Management Engine (FME), it introduces sysfs interfaces to
report different error detected by the hardware, and allow
user to clear errors or inject error for testing purpose.

Signed-off-by: Luwei Kang <[email protected]>
Signed-off-by: Ananda Ravuri <[email protected]>
Signed-off-by: Xu Yilun <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>

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fpga: dfl: afu: add error reporting support.

Error reporting is one important private feature, it reports error
detected on port and accelerated function unit (AFU). It introduces
several sysfs inte

fpga: dfl: afu: add error reporting support.

Error reporting is one important private feature, it reports error
detected on port and accelerated function unit (AFU). It introduces
several sysfs interfaces to allow userspace to check and clear
errors detected by hardware.

Signed-off-by: Xu Yilun <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>

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fpga manager: Adding FPGA Manager support for Xilinx zynqmp

This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.

Signed-off-by: Nava kishore Manne <[email protected]>
Reviewed-by: M

fpga manager: Adding FPGA Manager support for Xilinx zynqmp

This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.

Signed-off-by: Nava kishore Manne <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Michal Simek <[email protected]>

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fpga: add intel stratix10 soc fpga manager driver

Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel service layer driver
which does communicat

fpga: add intel stratix10 soc fpga manager driver

Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel service layer driver
which does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.

Signed-off-by: Alan Tull <[email protected]>
Signed-off-by: Richard Gong <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support

DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user m

fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support

DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to
unmap it after use, otherwise, driver will unmap them in device file
release operation.

Each AFU has its own rb tree to keep track of its mapped DMA regions.

Ioctl interfaces:
* DFL_FPGA_PORT_DMA_MAP
Do the dma mapping per user_addr and length provided by user.
Return iova in provided struct dfl_fpga_port_dma_map.

* DFL_FPGA_PORT_DMA_UNMAP
Unmap the dma region per iova provided by user.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: afu: add afu sub feature support

User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this M

fpga: dfl: afu: add afu sub feature support

User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this MMIO region could be accessed.

This patch adds support to enumerate the AFU MMIO region and expose it
to userspace via mmap file operation. Below interfaces are exposed to user:

Sysfs interface:
* /sys/class/fpga_region/<regionX>/<dfl-port.x>/afu_id
Read-only. Indicate which PR bitstream is programmed to this AFU.

Ioctl interfaces:
* DFL_FPGA_PORT_GET_INFO
Provide info to userspace on the number of supported region.
Only UAFU region is supported now.

* DFL_FPGA_PORT_GET_REGION_INFO
Provide region information, including access permission, region size,
offset from the start of device fd.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: add FPGA Accelerated Function Unit driver basic framework

On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
in

fpga: dfl: add FPGA Accelerated Function Unit driver basic framework

On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure (static FPGA region) via a Port. Port CSRs are
implemented separately from the AFU CSRs to provide control and
status of the Port. Once valid PR bitstream is programmed into
the AFU, it allows access to the AFU CSRs in the AFU MMIO space.

This patch only implements basic driver framework for AFU, including
device file operation framework.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: add fpga region platform driver for FME

This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.

Signed

fpga: dfl: add fpga region platform driver for FME

This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: add fpga bridge platform driver for FME

This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.

Signed-off-by: Tim

fpga: dfl: add fpga bridge platform driver for FME

This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: add fpga manager platform driver for FME

This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.

S

fpga: dfl: add fpga manager platform driver for FME

This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Kang Luwei <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: fme: add partial reconfiguration sub feature support

Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Uni

fpga: dfl: fme: add partial reconfiguration sub feature support

Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).

It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga) for PR
operation once PR request received via ioctl. Below user space interface
is exposed by this sub feature.

Ioctl interface:
* DFL_FPGA_FME_PORT_PR
Do partial reconfiguration per information from userspace, including
target port(AFU), buffer size and address info. It returns error code
to userspace if failed. For detailed PR error information, user needs
to read fpga-mgr's status sysfs interface.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Kang Luwei <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: dfl: add FPGA Management Engine driver basic framework

The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. F

fpga: dfl: add FPGA Management Engine driver basic framework

The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device created by
DFL framework.

This patch adds the basic framework of FME platform driver. It defines
sub feature drivers to handle the different sub features, including init,
uinit and ioctl. It also registers the file operations for the device file.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Kang Luwei <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: add FPGA DFL PCIe device driver

This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is ve

fpga: add FPGA DFL PCIe device driver

This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
both integrated (e.g. Intel Server Platform with In-package FPGA) and
discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Zhang Yi <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: add device feature list support

Device Feature List (DFL) defines a feature list structure that creates
a linked list of feature headers within the MMIO space to provide an
extensible way of a

fpga: add device feature list support

Device Feature List (DFL) defines a feature list structure that creates
a linked list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device Feature List.

Usually there will be different features and their sub features linked into
the DFL. This code provides common APIs for feature enumeration, it creates
a container device (FPGA base region), walks through the DFLs and creates
platform devices for feature devices (Currently it only supports two
different feature devices, FPGA Management Engine (FME) and Port which
the Accelerator Function Unit (AFU) connected to). In order to enumerate
the DFLs, the common APIs required low level driver to provide necessary
enumeration information (e.g. address for each device feature list for
given device) and fill it to the dfl_fpga_enum_info data structure. Please
refer to below description for APIs added for enumeration.

Functions for enumeration information preparation:
*dfl_fpga_enum_info_alloc
allocate enumeration information data structure.

*dfl_fpga_enum_info_add_dfl
add a device feature list to dfl_fpga_enum_info data structure.

*dfl_fpga_enum_info_free
free dfl_fpga_enum_info data structure and related resources.

Functions for feature device enumeration:
*dfl_fpga_feature_devs_enumerate
enumerate feature devices and return container device.

*dfl_fpga_feature_devs_remove
remove feature devices under given container device.

Signed-off-by: Tim Whisonant <[email protected]>
Signed-off-by: Enno Luebbers <[email protected]>
Signed-off-by: Shiva Rao <[email protected]>
Signed-off-by: Christopher Rauer <[email protected]>
Signed-off-by: Zhang Yi <[email protected]>
Signed-off-by: Xiao Guangrong <[email protected]>
Signed-off-by: Wu Hao <[email protected]>
Acked-by: Alan Tull <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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fpga: lattice machxo2: Add Lattice MachXO2 support

This patch adds support to the FPGA manager for programming
MachXO2 device’s internal flash memory, via slave SPI.

Signed-off-by: Paolo Pisati <p.

fpga: lattice machxo2: Add Lattice MachXO2 support

This patch adds support to the FPGA manager for programming
MachXO2 device’s internal flash memory, via slave SPI.

Signed-off-by: Paolo Pisati <[email protected]>
[[email protected]: use existing FPGA mgr API]
Signed-off-by: Alan Tull <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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