Changes in Makefile

104712a0 - fpga: xilinx-selectmap: add new driver

Thu, 21 Mar 2024 22:04:35 +0000

fpga: xilinx-selectmap: add new driverXilinx 7 series FPGA can be programmed using a parallel port namedthe SelectMAP interface in the datasheet. This interface is compatiblewith the i.MX6 EIM bus controller but other types of external memorymapped parallel bus might work.xilinx-selectmap currently only supports the x8 mode where data is loadedat one byte per rising edge of the clock, with the MSb of each bytepresented to the D0 pin.Signed-off-by: Charles Perry [yilun.xu@linux.intel.com: replace data type of i from u32 to size_t]Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

a52e3a9d - fpga: xilinx-spi: extract a common driver core

Thu, 21 Mar 2024 22:04:33 +0000

fpga: xilinx-spi: extract a common driver coreFactor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE)protocol in xilinx-core so that it can be reused for another driver.This commit does not change anything functionally to xilinx-spi.xilinx-core expects drivers to provide a write(const char* buf,size_t count) function that performs the actual write to the device,as well as a struct device* for resource management.Signed-off-by: Charles Perry Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20240321220447.3260065-2-charles.perry@savoirfairelinux.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

3969f645 - fpga: add configuration for the FPGA KUnit test suites.

Tue, 18 Jul 2023 13:03:04 +0000

fpga: add configuration for the FPGA KUnit test suites.Add configuration for the KUnit test suites for the core componentsof the FPGA subsystem.Signed-off-by: Marco Pagani Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20230718130304.87048-5-marpagan@redhat.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

463dd43b - fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager

Tue, 25 Oct 2022 05:39:46 +0000

fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA managerAdd support to the FPGA manager for programming Lattice ECP5 FPGA overslave SPI sysCONFIG interface.sysCONFIG interface core functionality is separate from both ECP5 andSPI specifics, so support for other FPGAs with different port types canbe added in the future.Signed-off-by: Ivan Bornyakov Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20221025053947.2737-2-i.bornyakov@metrotek.ru[yilun.xu@intel.com: remove redundant blank line after kmemdup]Signed-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

5f8d4a90 - fpga: microchip-spi: add Microchip MPF FPGA manager

Thu, 23 Jun 2022 16:32:46 +0000

fpga: microchip-spi: add Microchip MPF FPGA managerAdd support to the FPGA manager for programming Microchip PolarfireFPGAs over slave SPI interface with .dat formatted bitsream image.Signed-off-by: Ivan Bornyakov Reviewed-by: Conor Dooley Tested-by: Conor Dooley Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20220623163248.3672-4-i.bornyakov@metrotek.ruSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

bdf86d0e - fpga: m10bmc-sec: create max10 bmc secure update

Mon, 06 Jun 2022 16:00:35 +0000

fpga: m10bmc-sec: create max10 bmc secure updateCreate a sub-driver for the FPGA Card BMC in order to support secureupdates. This patch creates the Max10 BMC Secure Update driver andprovides sysfs files for displaying the root entry hashes (REH) for theFPGA static region (SR), the FPGA Partial Reconfiguration (PR) region,and the card BMC.The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmwareand FPGA images are authenticated using ECDSA before loading and executingon the card. Code Signing Keys (CSK) are used to sign images. CSKs aresigned by a root key. The root entry hash is created from the root publickey.The RoT provides authentication by storing an REH bitstream to a write-oncelocation. Image signatures are verified against the hash.Reviewed-by: Tom Rix Tested-by: Tianfei Zhang Signed-off-by: Russ Weight Link: https://lore.kernel.org/r/20220606160038.846236-3-russell.h.weight@intel.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

baf7d27d - fpga: Use tab instead of space indentation

Sat, 23 Apr 2022 17:02:34 +0000

fpga: Use tab instead of space indentationIn FPGA Makefile has both space and tab indentation, tomake them align use tab instead of space indentation.Signed-off-by: Nava kishore Manne Link: https://lore.kernel.org/r/20220423170235.2115479-5-nava.manne@xilinx.comSigned-off-by: Xu Yilun List of files: /linux-6.15/drivers/fpga/Makefile

01c54e62 - fpga: versal-fpga: Add versal fpga manager driver

Sat, 26 Jun 2021 15:52:48 +0000

fpga: versal-fpga: Add versal fpga manager driverAdd support for Xilinx Versal FPGA manager.PDI source type can be DDR, OCM, QSPI flash etc..But driver allocates memory always from DDR, Since driver supports onlyDDR source type.Reviewed-by: Moritz Fischer Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Nava kishore Manne Link: https://lore.kernel.org/r/20210626155248.5004-6-nava.manne@xilinx.comSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

56172ab3 - fpga: dfl: add support for N3000 Nios private feature

Thu, 07 Jan 2021 04:37:13 +0000

fpga: dfl: add support for N3000 Nios private featureThis patch adds support for the Nios handshake private feature on IntelPAC (Programmable Acceleration Card) N3000.The Nios is the embedded processor on the FPGA card. This private featureprovides a handshake interface to FPGA Nios firmware, which receivesretimer configuration command from host and executes via an internal SPImaster (spi-altera). When Nios finishes the configuration, host takes overthe ownership of the SPI master to control an Intel MAX10 BMC (BoardManagement Controller) Chip on the SPI bus.For Nios firmware handshake part, this driver requests the retimerconfiguration for Nios firmware on probe, and adds some sysfs nodes foruser to query the onboard retimer's working mode and Nios firmwareversion.For SPI part, this driver adds a spi-altera platform device as well asthe MAX10 BMC spi slave info. A spi-altera driver will be matched tohandle the following SPI work.[mdf@kernel.org: Fixed up ABI doc kernel release]Reviewed-by: Tom Rix Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Signed-off-by: Matthew Gerlach Signed-off-by: Russ Weight Signed-off-by: YueHaibing Link: https://lore.kernel.org/r/20210107043714.991646-8-mdf@kernel.orgSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

724142f8 - fpga: dfl: fme: add performance reporting support

Mon, 27 Apr 2020 01:06:23 +0000

fpga: dfl: fme: add performance reporting supportThis patch adds support for performance reporting private featurefor FPGA Management Engine (FME). Now it supports several differentperformance counters, including 'basic', 'cache', 'fabric', 'vtd'and 'vtd_sip'. It allows user to use standard linux tools to accessthese performance counters.e.g. List all events by "perf list" perf list | grep fme dfl_fme0/cache_read_hit/ [Kernel PMU event] dfl_fme0/cache_read_miss/ [Kernel PMU event] ... dfl_fme0/fab_mmio_read/ [Kernel PMU event] dfl_fme0/fab_mmio_write/ [Kernel PMU event] ... dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event] dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event] dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event] ... dfl_fme0/clock [Kernel PMU event] ...e.g. check increased counter value after run one application using"perf stat" command. perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test Performance counter stats for './test': 1 dfl_fme0/fab_mmio_read/ 2 dfl_fme0/fab_mmio_write/ 1.009496520 seconds time elapsedPlease note that fabric counters support both fab_* and fab_port_*, butactually they are sharing one set of performance counters in hardware.If user wants to monitor overall data events on fab_* then fab_port_*can't be supported at the same time, see example below:perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/ Performance counter stats for 'system wide': 0 dfl_fme0/fab_mmio_read/ dfl_fme0/fab_port_mmio_write,portid=0/ 2.141064085 seconds time elapsedSigned-off-by: Luwei Kang Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.comSigned-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

cb3c2c47 - fpga: dfl: fme: add global error reporting support

Mon, 12 Aug 2019 02:50:03 +0000

fpga: dfl: fme: add global error reporting supportThis patch adds support for global error reporting for FPGAManagement Engine (FME), it introduces sysfs interfaces toreport different error detected by the hardware, and allowuser to clear errors or inject error for testing purpose.Signed-off-by: Luwei Kang Signed-off-by: Ananda Ravuri Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Moritz Fischer List of files: /linux-6.15/drivers/fpga/Makefile

44d24753 - fpga: dfl: afu: add error reporting support.

Mon, 12 Aug 2019 02:50:01 +0000

fpga: dfl: afu: add error reporting support.Error reporting is one important private feature, it reports errordetected on port and accelerated function unit (AFU). It introducesseveral sysfs interfaces to allow userspace to check and clearerrors detected by hardware.Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Moritz Fischer List of files: /linux-6.15/drivers/fpga/Makefile

c09f7471 - fpga manager: Adding FPGA Manager support for Xilinx zynqmp

Mon, 15 Apr 2019 07:17:48 +0000

fpga manager: Adding FPGA Manager support for Xilinx zynqmpThis patch adds FPGA Manager support for the XilinxZynqMP chip.Signed-off-by: Nava kishore Manne Reviewed-by: Moritz Fischer Acked-by: Alan Tull Signed-off-by: Michal Simek List of files: /linux-6.15/drivers/fpga/Makefile

e7eef1d7 - fpga: add intel stratix10 soc fpga manager driver

Tue, 13 Nov 2018 18:14:04 +0000

fpga: add intel stratix10 soc fpga manager driverAdd driver for reconfiguring Intel Stratix10 SoC FPGA devices.This driver communicates through the Intel service layer driverwhich does communication with privileged hardware (that does theFPGA programming) through a secure mailbox.Signed-off-by: Alan Tull Signed-off-by: Richard Gong Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

fa8dda1e - fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support

Sat, 30 Jun 2018 00:53:35 +0000

fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls supportDMA memory regions are required for Accelerated Function Unit (AFU) usage.These two ioctls allow user space applications to map user memory regionsfor dma, and unmap them after use. Iova is returned from driver to userspace application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs tounmap it after use, otherwise, driver will unmap them in device filerelease operation.Each AFU has its own rb tree to keep track of its mapped DMA regions.Ioctl interfaces:* DFL_FPGA_PORT_DMA_MAP Do the dma mapping per user_addr and length provided by user. Return iova in provided struct dfl_fpga_port_dma_map.* DFL_FPGA_PORT_DMA_UNMAP Unmap the dma region per iova provided by user.Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

857a2622 - fpga: dfl: afu: add afu sub feature support

Sat, 30 Jun 2018 00:53:34 +0000

fpga: dfl: afu: add afu sub feature supportUser Accelerated Function Unit sub feature exposes the MMIO region ofthe AFU. After valid PR bitstream is programmed and the port is enabled,then this MMIO region could be accessed.This patch adds support to enumerate the AFU MMIO region and expose itto userspace via mmap file operation. Below interfaces are exposed to user:Sysfs interface:* /sys/class/fpga_region///afu_id Read-only. Indicate which PR bitstream is programmed to this AFU.Ioctl interfaces:* DFL_FPGA_PORT_GET_INFO Provide info to userspace on the number of supported region. Only UAFU region is supported now.* DFL_FPGA_PORT_GET_REGION_INFO Provide region information, including access permission, region size, offset from the start of device fd.Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

1a1527cf - fpga: dfl: add FPGA Accelerated Function Unit driver basic framework

Sat, 30 Jun 2018 00:53:30 +0000

fpga: dfl: add FPGA Accelerated Function Unit driver basic frameworkOn DFL FPGA devices, the Accelerated Function Unit (AFU), can bereprogrammed for different functions. It connects to the FPGAinfrastructure (static FPGA region) via a Port. Port CSRs areimplemented separately from the AFU CSRs to provide control andstatus of the Port. Once valid PR bitstream is programmed intothe AFU, it allows access to the AFU CSRs in the AFU MMIO space.This patch only implements basic driver framework for AFU, includingdevice file operation framework.Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

bb61b9be - fpga: dfl: add fpga region platform driver for FME

Sat, 30 Jun 2018 00:53:28 +0000

fpga: dfl: add fpga region platform driver for FMEThis patch adds fpga region platform driver for FPGA Management Engine.It register an fpga region with given fpga manager / bridge device.Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Wu Hao Acked-by: Alan Tull Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

de892dff - fpga: dfl: add fpga bridge platform driver for FME

Sat, 30 Jun 2018 00:53:27 +0000

fpga: dfl: add fpga bridge platform driver for FMEThis patch adds fpga bridge platform driver for FPGA Management Engine.It implements the enable_set callback for fpga bridge.Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Wu Hao Acked-by: Alan Tull Acked-by: Moritz Fischer Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile

af275ec6 - fpga: dfl: add fpga manager platform driver for FME

Sat, 30 Jun 2018 00:53:25 +0000

fpga: dfl: add fpga manager platform driver for FMEThis patch adds fpga manager driver for FPGA Management Engine (FME). Itimplements fpga_manager_ops for FPGA Partial Reconfiguration function.Signed-off-by: Tim Whisonant Signed-off-by: Enno Luebbers Signed-off-by: Shiva Rao Signed-off-by: Christopher Rauer Signed-off-by: Kang Luwei Signed-off-by: Xiao Guangrong Signed-off-by: Wu Hao Acked-by: Alan Tull Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/fpga/Makefile