clk: rockchip: Add clock controller for the RK3562

Add the clock tree definition for the new RK3562 SoC.

Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Tao Huang <huangtao@r

clk: rockchip: Add clock controller for the RK3562

Add the clock tree definition for the new RK3562 SoC.

Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Tao Huang <[email protected]>
Signed-off-by: Sugar Zhang <[email protected]>
Signed-off-by: Kever Yang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[dropped non-working module code, cleaned up init a bit to address
build failure reported from kernel test robot
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ ]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: rk3528: Add reset lookup table

In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver
for RK3528 SoC") only the dt-binding header was added for the reset
controller f

clk: rockchip: rk3528: Add reset lookup table

In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver
for RK3528 SoC") only the dt-binding header was added for the reset
controller for the RK3528 SoC.

Add a reset lookup table generated from the SRST symbols used by vendor
linux-6.1-stan-rkr5 kernel to complete support for the reset controller.

Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: Add clock controller driver for RK3528 SoC

Add clock tree definition for RK3528. Similar to previous Rockchip
SoCs, clock controller of RK3528 is combined with the reset controller.
W

clk: rockchip: Add clock controller driver for RK3528 SoC

Add clock tree definition for RK3528. Similar to previous Rockchip
SoCs, clock controller of RK3528 is combined with the reset controller.
We omit the reset part for now since it's hard to test it without
support for other basic peripherals.

Signed-off-by: Yao Zi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: implement linked gate clock support

Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These clock
gates wil

clk: rockchip: implement linked gate clock support

Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These clock
gates will only have a running output clock when all of the following
conditions are met:

1. the parent clock is enabled
2. the enable bit is set correctly
3. the linked clock is enabled

To handle them this code registers them as a normal gate type clock,
which takes care of condition 1 + 2. The linked clock is handled by
using runtime PM clocks. Handling it via runtime PM requires setting
up a struct device for each of these clocks with a driver attached
to use the correct runtime PM operations. Thus the complete handling
of these clocks has been moved into its own driver.

Signed-off-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: Add clock controller for the RK3576

Add the clock and reset tree definitions for the new RK3576
SoC.

As opposed to the other rockchip CRU drivers, the GRF node is looked up
via compa

clk: rockchip: Add clock controller for the RK3576

Add the clock and reset tree definitions for the new RK3576
SoC.

As opposed to the other rockchip CRU drivers, the GRF node is looked up
via compatible instead of a phandle, which simplifies the device tree
bindings.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: YouMin Chen <[email protected]>
Signed-off-by: Liang Chen <[email protected]>
Signed-off-by: Sugar Zhang <[email protected]>
Signed-off-by: Detlev Casanova <[email protected]>
Reviewed-by: Elaine Zhang <[email protected]>
Tested-by: Shawn Lin <[email protected]>
Acked-by: Dragan Simic <[email protected]>
Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com
[dropped additional blank line at EOF in rst-rk3576.c
dropped the whole (non-)working as module part]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for the RK3588

Add full clock controller support RK3588.

[rebase, integrate fixes from Wyon and Finley, add missing frequencies
to PLL lookup table, update comm

clk: rockchip: add clock controller for the RK3588

Add full clock controller support RK3588.

[rebase, integrate fixes from Wyon and Finley, add missing frequencies
to PLL lookup table, update commit message, add GATE_LINK clocks which
downstream handles in its own driver with one DT node per clock]

Signed-off-by: Wyon Bi <[email protected]>
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[dropped module stuff after talking to Sebastian]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: Add clock controller support for RV1126 SoC

Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.

This patch is trying to add minimal Clock-Architecture Diagr

clk: rockchip: Add clock controller support for RV1126 SoC

Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.

This patch is trying to add minimal Clock-Architecture Diagram's
inferred from [1] authored by Finley Xiao.

[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c

Cc: [email protected]
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for rk3568

Add the clock tree definition for the new rk3568 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <kever.yang@rock-

clk: rockchip: add clock controller for rk3568

Add the clock tree definition for the new rk3568 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: fix the clk config to support module build

use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
t

clk: rockchip: fix the clk config to support module build

use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
to support building Rk3399 SoC clock driver as module.

Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: Add clock controller for the rk3308

Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Heiko Stuebner <heiko

clk: rockchip: Add clock controller for the rk3308

Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: Finley Xiao <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for px30

Add the clock tree definition for the new px30 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]

clk: rockchip: add clock controller for px30

Add the clock tree definition for the new px30 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add support for half divider

The new Rockchip socs have optional half divider:
The formula is shown as:
freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.

So w

clk: rockchip: add support for half divider

The new Rockchip socs have optional half divider:
The formula is shown as:
freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.

So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: remove deprecated gate-clk code and dt-binding

Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specif

clk: rockchip: remove deprecated gate-clk code and dt-binding

Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.

As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.

That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.

Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.

Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license

Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.

For non */uapi/* files that summary was:

SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139

and resulted in the first patch in this series.

If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:

SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930

and resulted in the second patch in this series.

- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:

SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1

and that resulted in the third patch in this series.

- when the two scanners agreed on the detected license(s), that became
the concluded license(s).

- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.

- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).

- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.

- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct

This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Philippe Ombredanne <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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clk: rockchip: add clock controller for rk3128

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Si

clk: rockchip: add clock controller for rk3128

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: rename RK1108 to RV1108

Rockchip finally named the SOC as RV1108, so change it.

Signed-off-by: Andy Yan <[email protected]>

[include rename in rk1108.dtsi to prevent compile e

clk: rockchip: rename RK1108 to RV1108

Rockchip finally named the SOC as RV1108, so change it.

Signed-off-by: Andy Yan <[email protected]>

[include rename in rk1108.dtsi to prevent compile errors]
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for rk3328

Add the clock tree definition for the new rk3328 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <heiko@snte

clk: rockchip: add clock controller for rk3328

Add the clock tree definition for the new rk3328 SoC.

Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add a clock-type for muxes based in the grf

Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the general regist

clk: rockchip: add a clock-type for muxes based in the grf

Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the general register
files. Add a clock-type that can control these as well, so that we
don't need to work around them being absent.

Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for rk1108

Add the clock tree definition and driver for rk1108 SoC.

Signed-off-by: Shawn Lin <[email protected]>
Tested-by: Jacob Chen <jacob2.chen@rock-c

clk: rockchip: add clock controller for rk1108

Add the clock tree definition and driver for rk1108 SoC.

Signed-off-by: Shawn Lin <[email protected]>
Tested-by: Jacob Chen <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add new clock-type for the ddrclk

Changing the rate of the DDR clock needs special care, as the DDR
is of course in use and will react badly if the rate changes under it.

Over time d

clk: rockchip: add new clock-type for the ddrclk

Changing the rate of the DDR clock needs special care, as the DDR
is of course in use and will react badly if the rate changes under it.

Over time different approaches to handle that were used.

Past SoCs like the rk3288 and before would store some code in SRAM
while the rk3368 used a SCPI variant and let a coprocessor handle that.

New rockchip platforms like the rk3399 have a dcf controller to do ddr
frequency scaling, and support for this controller will be implemented
in the arm-trusted-firmware.

This new clock-type should over time handle all these methods for
handling DDR rate changes, but right now it will concentrate on the
SIP interface used to talk to ARM trusted firmware.

The SIP interface counterpart was merged from pull-request #684 [0]
into the upstream arm-trusted-firmware codebase.

[0] https://github.com/ARM-software/arm-trusted-firmware/pull/684

Signed-off-by: Lin Huang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for the RK3399

Add the clock tree definition for the new RK3399 SoC.

Signed-off-by: Xing Zheng <[email protected]>
Signed-off-by: Heiko Stuebner <heiko@sn

clk: rockchip: add clock controller for the RK3399

Add the clock tree definition for the new RK3399 SoC.

Signed-off-by: Xing Zheng <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for rk3228

Add the clock tree definition for the new rk3228 SoC.

Signed-off-by: Jeffy Chen <[email protected]>
Signed-off-by: Heiko Stuebner <heiko@sntec

clk: rockchip: add clock controller for rk3228

Add the clock tree definition for the new rk3228 SoC.

Signed-off-by: Jeffy Chen <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng <[email protected]>
Signed-off-by: Heiko Stuebner <heiko@sntech

clk: rockchip: add clock controller for rk3036

Add the clock tree definition for the new rk3036 SoC.

Signed-off-by: Xing Zheng <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>

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clk: rockchip: add rk3368 clock controller

Describe the clock tree and software resets of the rk3368 ARM64 SoC

Signed-off-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <sboyd@cod

clk: rockchip: add rk3368 clock controller

Describe the clock tree and software resets of the rk3368 ARM64 SoC

Signed-off-by: Heiko Stuebner <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: rockchip: add support for phase inverters

Most Rockchip socs have optional phase inverters connected to some
clocks that move the clock-phase by 180 degrees.

Signed-off-by: Heiko Stuebner <hei

clk: rockchip: add support for phase inverters

Most Rockchip socs have optional phase inverters connected to some
clocks that move the clock-phase by 180 degrees.

Signed-off-by: Heiko Stuebner <[email protected]>
[[email protected]: Dropped lazy part of commit text]
Signed-off-by: Stephen Boyd <[email protected]>

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