clk: meson: c3: add c3 clock peripherals controller driver

Add the C3 peripherals clock controller driver in the C3 SoC family.

[jbrunet: fix Kconfig select order and probe function name]
Co-develo

clk: meson: c3: add c3 clock peripherals controller driver

Add the C3 peripherals clock controller driver in the C3 SoC family.

[jbrunet: fix Kconfig select order and probe function name]
Co-developed-by: Chuan Liu <[email protected]>
Signed-off-by: Chuan Liu <[email protected]>
Signed-off-by: Xianwei Zhao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: c3: add support for the C3 SoC PLL clock

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.

[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu <chuan.liu

clk: meson: c3: add support for the C3 SoC PLL clock

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.

[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu <[email protected]>
Signed-off-by: Chuan Liu <[email protected]>
Signed-off-by: Xianwei Zhao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add vclk driver

The VCLK and VCLK_DIV clocks have supplementary bits.

The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented

clk: meson: add vclk driver

The VCLK and VCLK_DIV clocks have supplementary bits.

The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.

The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK_SET_RATE_GATE it ensures
the rate is set while the divider is disabled and in reset mode.

The VCLK_DIV enable bit isn't implemented as a gate since it's part
of the divider logic and vendor does this exact sequence to ensure
the divider is correctly set.

Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

Add the peripherals clock controller driver in the S4 SoC family.

[jbrunet: remove extra new line at end of s4-peripherals

clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

Add the peripherals clock controller driver in the S4 SoC family.

[jbrunet: remove extra new line at end of s4-peripherals.h]
Signed-off-by: Yu Tu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Add the S4 PLL clock controller driver in the S4 SoC family.

Signed-off-by: Yu Tu <[email protected]>
Link: https://lore.kernel.org/r

clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Add the S4 PLL clock controller driver in the S4 SoC family.

Signed-off-by: Yu Tu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: introduce meson-clkc-utils

Let's introduce a new module called meson-clkc-utils that
will contain shared utility functions for all Amlogic clock
controller drivers.

The first utility fu

clk: meson: introduce meson-clkc-utils

Let's introduce a new module called meson-clkc-utils that
will contain shared utility functions for all Amlogic clock
controller drivers.

The first utility function is a replacement of of_clk_hw_onecell_get
in order to get rid of the NR_CLKS define in all Amlogic clock
drivers.

The goal is to move all duplicate probe and init code in this module.

[jbrunet: Fixed MODULE_LICENCE checkpatch warning]
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

Introduce Peripherals clock controller for Amlogic A1 SoC family.

A1 SoC has four clock controllers on the board: PLL, Peripherals

clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

Introduce Peripherals clock controller for Amlogic A1 SoC family.

A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,
and Audio.
This patchset adds support for Amlogic A1 Peripherals clock driver and
allows to generate clocks for all A1 SoC peripheral IPs.

Signed-off-by: Jian Hu <[email protected]>
Signed-off-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: a1: add Amlogic A1 PLL clock controller driver

Introduce PLL clock controller for Amlogic A1 SoC family.
The clock unit is an APB slave module that is designed for generating all
of the

clk: meson: a1: add Amlogic A1 PLL clock controller driver

Introduce PLL clock controller for Amlogic A1 SoC family.
The clock unit is an APB slave module that is designed for generating all
of the internal and system clocks.
The SoC uses an external 24MHz crystal; there are 4 internal PLLs:
SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources.

Signed-off-by: Jian Hu <[email protected]>
Signed-off-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller

The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the
MMCBUS registers. There is no public documentation, but the u

clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller

The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the
MMCBUS registers. There is no public documentation, but the u-boot GPL
sources from the Amlogic BSP show that the DDR clock controller is
identical on all three SoCs:
#define CFG_DDR_CLK 792
#define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24)
#define CFG_PLL_N 1
#define CFG_PLL_OD 1

// from set_ddr_clock:
t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0)
writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL);
writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL);

// from hx_ddr_power_down_enter: shut down DDR PLL
writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL);

do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0)

This translates to:
- AM_DDR_PLL_CNTL[29] is the reset bit
- AM_DDR_PLL_CNTL[30] is the enable bit
- AM_DDR_PLL_CNTL[31] is the lock bit
- AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits
based on the start of the n value)
- AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits
based on the start of the od)
- AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based
on other PLLs on this SoC)

Add a driver for this PLL setup because it's used as one of the inputs
of the audio clocks. There may be more clocks inside that clock
controller - those can be added in subsequent patches.

Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add g12a cpu dynamic divider driver

Add a clock driver for the cpu dynamic divider, this divider needs
to have a flag set before setting the divider value then removed
while writing the

clk: meson: add g12a cpu dynamic divider driver

Add a clock driver for the cpu dynamic divider, this divider needs
to have a flag set before setting the divider value then removed
while writing the new value to the register.

This drivers implements this behavior and will be used essentially
on the Amlogic G12A and G12B SoCs for cpu clock trees.

Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: remove clk input helper

The clk input function which allows clock controllers to register a bypass
clock from a clock producer is no longer needed anymore since meson clock
controllers h

clk: meson: remove clk input helper

The clk input function which allows clock controllers to register a bypass
clock from a clock producer is no longer needed anymore since meson clock
controllers have migrated to a new parent allocation method.

Signed-off-by: Alexandre Mergnat <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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clk: meson: Add G12A AO Clock + Reset Controller

Add the Amlogic G12A AO Clock and Reset controller driver handling
generation of Always-On clocks :
- AO Clocks and Reset for Always-On modules
- 32K

clk: meson: Add G12A AO Clock + Reset Controller

Add the Amlogic G12A AO Clock and Reset controller driver handling
generation of Always-On clocks :
- AO Clocks and Reset for Always-On modules
- 32K Generation for USB and CEC
- SAR ADC controller clock

Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Jerome Brunet <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: factorise meson64 peripheral clock controller drivers

The function used to probe the peripheral clock controller of the arm64
amlogic SoCs is mostly the same. We now have 3 of those cont

clk: meson: factorise meson64 peripheral clock controller drivers

The function used to probe the peripheral clock controller of the arm64
amlogic SoCs is mostly the same. We now have 3 of those controllers so
it is time to factorize things a bit.

Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: g12a: add peripheral clock controller

Add the peripheral clock controller found in the g12a SoC family

Signed-off-by: Jian Hu <[email protected]>
Signed-off-by: Neil Armstrong <narmst

clk: meson: g12a: add peripheral clock controller

Add the peripheral clock controller found in the g12a SoC family

Signed-off-by: Jian Hu <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: rework and clean drivers dependencies

Initially, the meson clock directory only hosted 2 controllers drivers,
for meson8 and gxbb. At the time, both used the same set of clock drivers
so

clk: meson: rework and clean drivers dependencies

Initially, the meson clock directory only hosted 2 controllers drivers,
for meson8 and gxbb. At the time, both used the same set of clock drivers
so managing the dependencies was not a big concern.

Since this ancient time, entropy did its job, controllers with different
requirement and specific clock drivers have been added. Unfortunately, we
did not do a great job at managing the dependencies between the
controllers and the different clock drivers. Some drivers, such as
clk-phase or vid-pll-div, are compiled even if they are useless on the
target (meson8). As we are adding new controllers, we need to be able to
pick a driver w/o pulling the whole thing.

The patch aims to clean things up by:
* providing a dedicated CONFIG_ for each clock drivers
* allowing clock drivers to be compiled as a modules, if possible
* stating explicitly which drivers are required by each controller.

Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: gxbb-ao: replace cec-32k with the dual divider

Replace the cec-32k clock of gxbb-ao with the simpler dual divider
driver. The dual divider implements only the dividing part. All the
othe

clk: meson: gxbb-ao: replace cec-32k with the dual divider

Replace the cec-32k clock of gxbb-ao with the simpler dual divider
driver. The dual divider implements only the dividing part. All the
other bits are now exposed using simple elements, such as gates and
muxes

Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: add dual divider clock driver

Add the dual divider driver. This special divider make a weighted
average between 2 dividers to reach fractional divider values.

Signed-off-by: Jerome Brun

clk: meson: add dual divider clock driver

Add the dual divider driver. This special divider make a weighted
average between 2 dividers to reach fractional divider values.

Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: add clk-input helper function

Add the clock input helper function. Several amlogic clock controllers
will now be registering bypass clock input. Instead of copying this
code in every of

clk: meson: add clk-input helper function

Add the clock input helper function. Several amlogic clock controllers
will now be registering bypass clock input. Instead of copying this
code in every of them, let's make an helper function for it

Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
[narmstrong: fixed up to apply on Makefile and clkc.h]
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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clk: meson: Add vid_pll divider driver

Add support the VID_PLL fully programmable divider used right after the
HDMI PLL clock source. It is used to achieve complex fractional division
with a program

clk: meson: Add vid_pll divider driver

Add support the VID_PLL fully programmable divider used right after the
HDMI PLL clock source. It is used to achieve complex fractional division
with a programmble bitfield.

Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Jerome Brunet <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]

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clk: meson: remove unused clk-audio-divider driver

clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <jbrunet@ba

clk: meson: remove unused clk-audio-divider driver

clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: axg: add the audio clock controller driver

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
differen

clk: meson: axg: add the audio clock controller driver

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add axg audio sclk divider driver

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific

clk: meson: add axg audio sclk divider driver

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
and the 'hi' value.

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add triple phase clock driver

Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control

clk: meson: add triple phase clock driver

Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control the phase provided to
the different element using the sample clock generator. This simplify
the usage of the sample clock generator a lot, without comprising the
ability of the SoC.

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add clk-phase clock driver

Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <jb

clk: meson: add clk-phase clock driver

Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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