Changes in Makefile

f06ac3ed - clk: meson: c3: add c3 clock peripherals controller driver

Wed, 22 May 2024 08:27:27 +0000

clk: meson: c3: add c3 clock peripherals controller driverAdd the C3 peripherals clock controller driver in the C3 SoC family.[jbrunet: fix Kconfig select order and probe function name]Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240522082727.3029656-6-xianwei.zhao@amlogic.comSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

8a9a129d - clk: meson: c3: add support for the C3 SoC PLL clock

Wed, 22 May 2024 08:27:26 +0000

clk: meson: c3: add support for the C3 SoC PLL clockAdd the C3 PLL clock controller driver for the Amlogic C3 SoC family.[jbrunet: fixed probe function name]Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.comSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

bb5aa085 - clk: meson: add vclk driver

Wed, 03 Apr 2024 07:46:33 +0000

clk: meson: add vclk driverThe VCLK and VCLK_DIV clocks have supplementary bits.The VCLK gate has a "SOFT RESET" bit to toggle after the wholeVCLK sub-tree rate has been set, this is implemented inthe gate enable callback.The VCLK_DIV clocks as enable and reset bits used to disableand reset the divider, associated with CLK_SET_RATE_GATE it ensuresthe rate is set while the divider is disabled and in reset mode.The VCLK_DIV enable bit isn't implemented as a gate since it's partof the divider logic and vendor does this exact sequence to ensurethe divider is correctly set.Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.orgSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

57b55c76 - clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

Mon, 04 Sep 2023 07:55:04 +0000

clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerAdd the peripherals clock controller driver in the S4 SoC family.[jbrunet: remove extra new line at end of s4-peripherals.h]Signed-off-by: Yu Tu Link: https://lore.kernel.org/r/20230904075504.23263-5-yu.tu@amlogic.comSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

e787c9c5 - clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Mon, 04 Sep 2023 07:55:03 +0000

clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverAdd the S4 PLL clock controller driver in the S4 SoC family.Signed-off-by: Yu Tu Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.comSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

230b6f3a - clk: meson: introduce meson-clkc-utils

Mon, 12 Jun 2023 09:57:18 +0000

clk: meson: introduce meson-clkc-utilsLet's introduce a new module called meson-clkc-utils thatwill contain shared utility functions for all Amlogic clockcontroller drivers.The first utility function is a replacement of of_clk_hw_onecell_getin order to get rid of the NR_CLKS define in all Amlogic clockdrivers.The goal is to move all duplicate probe and init code in this module.[jbrunet: Fixed MODULE_LICENCE checkpatch warning]Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.orgSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

84af9144 - clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

Tue, 23 May 2023 13:53:51 +0000

clk: meson: a1: add Amlogic A1 Peripherals clock controller driverIntroduce Peripherals clock controller for Amlogic A1 SoC family.A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,and Audio.This patchset adds support for Amlogic A1 Peripherals clock driver andallows to generate clocks for all A1 SoC peripheral IPs.Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230523135351.19133-7-ddrokosov@sberdevices.ruSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

28f3be51 - clk: meson: a1: add Amlogic A1 PLL clock controller driver

Tue, 23 May 2023 13:53:49 +0000

clk: meson: a1: add Amlogic A1 PLL clock controller driverIntroduce PLL clock controller for Amlogic A1 SoC family.The clock unit is an APB slave module that is designed for generating allof the internal and system clocks.The SoC uses an external 24MHz crystal; there are 4 internal PLLs:SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources.Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230523135351.19133-5-ddrokosov@sberdevices.ruSigned-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

64aa7008 - clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller

Sun, 17 Nov 2019 14:07:31 +0000

clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controllerThe Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in theMMCBUS registers. There is no public documentation, but the u-boot GPLsources from the Amlogic BSP show that the DDR clock controller isidentical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0)This translates to:- AM_DDR_PLL_CNTL[29] is the reset bit- AM_DDR_PLL_CNTL[30] is the enable bit- AM_DDR_PLL_CNTL[31] is the lock bit- AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value)- AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od)- AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC)Add a driver for this PLL setup because it's used as one of the inputsof the audio clocks. There may be more clocks inside that clockcontroller - those can be added in subsequent patches.Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

26d34431 - clk: meson: add g12a cpu dynamic divider driver

Wed, 31 Jul 2019 08:40:17 +0000

clk: meson: add g12a cpu dynamic divider driverAdd a clock driver for the cpu dynamic divider, this divider needsto have a flag set before setting the divider value then removedwhile writing the new value to the register.This drivers implements this behavior and will be used essentiallyon the Amlogic G12A and G12B SoCs for cpu clock trees.Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

e96c7612 - clk: meson: remove clk input helper

Thu, 25 Jul 2019 16:42:38 +0000

clk: meson: remove clk input helperThe clk input function which allows clock controllers to register a bypassclock from a clock producer is no longer needed anymore since meson clockcontrollers have migrated to a new parent allocation method.Signed-off-by: Alexandre Mergnat Signed-off-by: Jerome Brunet List of files: /linux-6.15/drivers/clk/meson/Makefile

ec8f24b7 - treewide: Add SPDX license identifier - Makefile/Kconfig

Sun, 19 May 2019 12:07:45 +0000

treewide: Add SPDX license identifier - Makefile/KconfigAdd SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any formThese files fall under the project license, GPL v2 only. The resulting SPDXlicense identifier is: GPL-2.0-onlySigned-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman List of files: /linux-6.15/drivers/clk/meson/Makefile

042f01bb - clk: meson: Add G12A AO Clock + Reset Controller

Tue, 12 Feb 2019 16:28:59 +0000

clk: meson: Add G12A AO Clock + Reset ControllerAdd the Amlogic G12A AO Clock and Reset controller driver handlinggeneration of Always-On clocks :- AO Clocks and Reset for Always-On modules- 32K Generation for USB and CEC- SAR ADC controller clockSigned-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

6682bd4d - clk: meson: factorise meson64 peripheral clock controller drivers

Fri, 01 Feb 2019 14:53:45 +0000

clk: meson: factorise meson64 peripheral clock controller driversThe function used to probe the peripheral clock controller of the arm64amlogic SoCs is mostly the same. We now have 3 of those controllers soit is time to factorize things a bit.Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

085a4ea9 - clk: meson: g12a: add peripheral clock controller

Fri, 01 Feb 2019 14:53:44 +0000

clk: meson: g12a: add peripheral clock controllerAdd the peripheral clock controller found in the g12a SoC familySigned-off-by: Jian Hu Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

889c2b7e - clk: meson: rework and clean drivers dependencies

Fri, 01 Feb 2019 12:58:41 +0000

clk: meson: rework and clean drivers dependenciesInitially, the meson clock directory only hosted 2 controllers drivers,for meson8 and gxbb. At the time, both used the same set of clock driversso managing the dependencies was not a big concern.Since this ancient time, entropy did its job, controllers with differentrequirement and specific clock drivers have been added. Unfortunately, wedid not do a great job at managing the dependencies between thecontrollers and the different clock drivers. Some drivers, such asclk-phase or vid-pll-div, are compiled even if they are useless on thetarget (meson8). As we are adding new controllers, we need to be able topick a driver w/o pulling the whole thing.The patch aims to clean things up by:* providing a dedicated CONFIG_ for each clock drivers* allowing clock drivers to be compiled as a modules, if possible* stating explicitly which drivers are required by each controller.Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

b249623f - clk: meson: gxbb-ao: replace cec-32k with the dual divider

Fri, 21 Dec 2018 16:02:38 +0000

clk: meson: gxbb-ao: replace cec-32k with the dual dividerReplace the cec-32k clock of gxbb-ao with the simpler dual dividerdriver. The dual divider implements only the dividing part. All theother bits are now exposed using simple elements, such as gates andmuxesSigned-off-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181221160239.26265-5-jbrunet@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

a8d552a6 - clk: meson: add dual divider clock driver

Fri, 21 Dec 2018 16:02:37 +0000

clk: meson: add dual divider clock driverAdd the dual divider driver. This special divider make a weightedaverage between 2 dividers to reach fractional divider values.Signed-off-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181221160239.26265-4-jbrunet@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

e456e6a1 - clk: meson: add clk-input helper function

Tue, 04 Dec 2018 16:58:18 +0000

clk: meson: add clk-input helper functionAdd the clock input helper function. Several amlogic clock controllerswill now be registering bypass clock input. Instead of copying thiscode in every of them, let's make an helper function for itSigned-off-by: Jerome Brunet Reviewed-by: Neil Armstrong [narmstrong: fixed up to apply on Makefile and clkc.h]Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181204165819.21541-2-jbrunet@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile

72dbb8c9 - clk: meson: Add vid_pll divider driver

Tue, 06 Nov 2018 14:57:34 +0000

clk: meson: Add vid_pll divider driverAdd support the VID_PLL fully programmable divider used right after theHDMI PLL clock source. It is used to achieve complex fractional divisionwith a programmble bitfield.Signed-off-by: Neil Armstrong Acked-by: Jerome Brunet Link: http://lkml.kernel.org/r/1541516257-16157-2-git-send-email-narmstrong@baylibre.com List of files: /linux-6.15/drivers/clk/meson/Makefile