clk: amlogic: axg-audio: revert reset implementation

The audio subsystem of axg based platform is not probing anymore.
This is due to the introduction of RESET_MESON_AUX and the config
not being ena

clk: amlogic: axg-audio: revert reset implementation

The audio subsystem of axg based platform is not probing anymore.
This is due to the introduction of RESET_MESON_AUX and the config
not being enabled with the default arm64 defconfig.

This brought another discussion around proper decoupling between
the clock and reset part. While this discussion gets sorted out,
revert back to the initial implementation.

This reverts
* commit 681ed497d676 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX")
* commit 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver")

Both are reverted with single change to avoid creating more compilation
problems.

Fixes: 681ed497d676 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX")
Cc: Arnd Bergmann <[email protected]>
Reported-by: Mark Brown <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Link: https://lore.kernel.org/r/20241128-clk-audio-fix-rst-missing-v2-1-cf437d1a73da@baylibre.com
Signed-off-by: Stephen Boyd <[email protected]>

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clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX

As in most cases, using 'imply' is wrong here and does not prevent
build failures since that code may not be visible to a built-in

clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX

As in most cases, using 'imply' is wrong here and does not prevent
build failures since that code may not be visible to a built-in
clk driver:

axg-audio.c:(.text+0x15c): undefined reference to `devm_meson_rst_aux_register'

Replace the incorrt 'imply' with the necessary 'depends on'.

Fixes: 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver")
Signed-off-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Jerome Brunet <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: amlogic: axg-audio: use the auxiliary reset driver

Remove the implementation of the reset driver in axg audio
clock driver and migrate to the one provided by the reset framework
on the auxiliar

clk: amlogic: axg-audio: use the auxiliary reset driver

Remove the implementation of the reset driver in axg audio
clock driver and migrate to the one provided by the reset framework
on the auxiliary bus

Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: c3: add c3 clock peripherals controller driver

Add the C3 peripherals clock controller driver in the C3 SoC family.

[jbrunet: fix Kconfig select order and probe function name]
Co-develo

clk: meson: c3: add c3 clock peripherals controller driver

Add the C3 peripherals clock controller driver in the C3 SoC family.

[jbrunet: fix Kconfig select order and probe function name]
Co-developed-by: Chuan Liu <[email protected]>
Signed-off-by: Chuan Liu <[email protected]>
Signed-off-by: Xianwei Zhao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: c3: add support for the C3 SoC PLL clock

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.

[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu <chuan.liu

clk: meson: c3: add support for the C3 SoC PLL clock

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.

[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu <[email protected]>
Signed-off-by: Chuan Liu <[email protected]>
Signed-off-by: Xianwei Zhao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF

In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.

The nocache option is removed fro

clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF

In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.

The nocache option is removed from following clocks:
- vclk2_sel
- vclk2_input
- vclk2_div
- vclk2
- vclk_div1
- vclk2_div2_en
- vclk2_div4_en
- vclk2_div6_en
- vclk2_div12_en
- vclk2_div2
- vclk2_div4
- vclk2_div6
- vclk2_div12
- cts_encl_sel

vclk2 and vclk2_div uses the newly introduced vclk regmap driver
to handle the enable and reset bits.

In order to set a rate on cts_encl via the vclk2 clock path,
the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
to keep CCF from selection a parent.
The parents of cts_encl_sel & vclk2_sel are expected to be defined
in DT or manually set by the display driver at some point.

The following clock scheme is to be used for DSI:

xtal
\_ gp0_pll_dco
\_ gp0_pll
|- vclk2_sel
| \_ vclk2_input
| \_ vclk2_div
| \_ vclk2
| \_ vclk2_div1
| \_ cts_encl_sel
| \_ cts_encl -> to VPU LCD Encoder
|- mipi_dsi_pxclk_sel
\_ mipi_dsi_pxclk_div
\_ mipi_dsi_pxclk -> to DSI controller

The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table
in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input.

The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the
DSI bitclock is the reference base clock to calculate the vclk2_div value
when pixel clock is set on the cts_encl endpoint.

Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: add vclk driver

The VCLK and VCLK_DIV clocks have supplementary bits.

The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented

clk: meson: add vclk driver

The VCLK and VCLK_DIV clocks have supplementary bits.

The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.

The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK_SET_RATE_GATE it ensures
the rate is set while the divider is disabled and in reset mode.

The VCLK_DIV enable bit isn't implemented as a gate since it's part
of the divider logic and vendor does this exact sequence to ensure
the divider is correctly set.

Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS

Without this, the newly added drivers fail to link:

aarch64-linux-ld: drivers/clk/meson/s4-pll.o: in function `meson_s4_pll_probe':
s4-pll.

clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS

Without this, the newly added drivers fail to link:

aarch64-linux-ld: drivers/clk/meson/s4-pll.o: in function `meson_s4_pll_probe':
s4-pll.c:(.text+0x13c): undefined reference to `meson_clk_hw_get'
aarch64-linux-ld: drivers/clk/meson/s4-peripherals.o: in function `meson_s4_periphs_probe':
s4-peripherals.c:(.text+0xb0): undefined reference to `meson_clk_hw_get'

Fixes: e787c9c55eda ("clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver")
Reviewed-by: Jerome Brunet <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[jbrunet: use 12 char for the Fixes as recommended ]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

Add the peripherals clock controller driver in the S4 SoC family.

[jbrunet: remove extra new line at end of s4-peripherals

clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

Add the peripherals clock controller driver in the S4 SoC family.

[jbrunet: remove extra new line at end of s4-peripherals.h]
Signed-off-by: Yu Tu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Add the S4 PLL clock controller driver in the S4 SoC family.

Signed-off-by: Yu Tu <[email protected]>
Link: https://lore.kernel.org/r

clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Add the S4 PLL clock controller driver in the S4 SoC family.

Signed-off-by: Yu Tu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossib

clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.

Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible

clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.

Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-5-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it i

clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.

Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Dmitry Rokosov <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-4-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];

clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_aoclk_data struct to finally get rid on the
NR_CLKS define.

[jbrunet: Fixed whitespace checkpatch warning]
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-3-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct cl

clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_eeclkc_data struct to finally get rid on the
NR_CLKS define.

Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: introduce meson-clkc-utils

Let's introduce a new module called meson-clkc-utils that
will contain shared utility functions for all Amlogic clock
controller drivers.

The first utility fu

clk: meson: introduce meson-clkc-utils

Let's introduce a new module called meson-clkc-utils that
will contain shared utility functions for all Amlogic clock
controller drivers.

The first utility function is a replacement of of_clk_hw_onecell_get
in order to get rid of the NR_CLKS define in all Amlogic clock
drivers.

The goal is to move all duplicate probe and init code in this module.

[jbrunet: Fixed MODULE_LICENCE checkpatch warning]
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

Introduce Peripherals clock controller for Amlogic A1 SoC family.

A1 SoC has four clock controllers on the board: PLL, Peripherals

clk: meson: a1: add Amlogic A1 Peripherals clock controller driver

Introduce Peripherals clock controller for Amlogic A1 SoC family.

A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,
and Audio.
This patchset adds support for Amlogic A1 Peripherals clock driver and
allows to generate clocks for all A1 SoC peripheral IPs.

Signed-off-by: Jian Hu <[email protected]>
Signed-off-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: a1: add Amlogic A1 PLL clock controller driver

Introduce PLL clock controller for Amlogic A1 SoC family.
The clock unit is an APB slave module that is designed for generating all
of the

clk: meson: a1: add Amlogic A1 PLL clock controller driver

Introduce PLL clock controller for Amlogic A1 SoC family.
The clock unit is an APB slave module that is designed for generating all
of the internal and system clocks.
The SoC uses an external 24MHz crystal; there are 4 internal PLLs:
SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources.

Signed-off-by: Jian Hu <[email protected]>
Signed-off-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: enable building as modules

Make it possible to build all clk drivers as modules, but default
remains built-in.

No functional changes.

Signed-off-by: Kevin Hilman <[email protected]>

clk: meson: enable building as modules

Make it possible to build all clk drivers as modules, but default
remains built-in.

No functional changes.

Signed-off-by: Kevin Hilman <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: meson: Kconfig: fix dependency for G12A

When building only G12A, ensure that VID_PLL_DIV clock driver is
selected, otherwise results in this build error:

ERROR: modpost: "meson_vid_pll_div_ro_

clk: meson: Kconfig: fix dependency for G12A

When building only G12A, ensure that VID_PLL_DIV clock driver is
selected, otherwise results in this build error:

ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined!

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Kevin Hilman <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: meson: make shipped controller configurable

Add the necessary bits so unnecessary amlogic clock controllers can be
compiled out. This allows to save a few kB when necessary.

Signed-off-by: Jer

clk: meson: make shipped controller configurable

Add the necessary bits so unnecessary amlogic clock controllers can be
compiled out. This allows to save a few kB when necessary.

Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: meson: add g12a cpu dynamic divider driver

Add a clock driver for the cpu dynamic divider, this divider needs
to have a flag set before setting the divider value then removed
while writing the

clk: meson: add g12a cpu dynamic divider driver

Add a clock driver for the cpu dynamic divider, this divider needs
to have a flag set before setting the divider value then removed
while writing the new value to the register.

This drivers implements this behavior and will be used essentially
on the Amlogic G12A and G12B SoCs for cpu clock trees.

Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: remove clk input helper

The clk input function which allows clock controllers to register a bypass
clock from a clock producer is no longer needed anymore since meson clock
controllers h

clk: meson: remove clk input helper

The clk input function which allows clock controllers to register a bypass
clock from a clock producer is no longer needed anymore since meson clock
controllers have migrated to a new parent allocation method.

Signed-off-by: Alexandre Mergnat <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: remove ee input bypass clocks

During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of

clk: meson: remove ee input bypass clocks

During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of this method are the duplicated clocks, means more string
comparison.

Specify parent directly with device-tree clock name.

Remove the bypass clock registration from the ee probe function.

Signed-off-by: Alexandre Mergnat <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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clk: meson: remove ao input bypass clocks

During probe, bypass clocks (i.e. ao-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of

clk: meson: remove ao input bypass clocks

During probe, bypass clocks (i.e. ao-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of this method are the duplicated clocks, means more string
comparison.

Specify parent directly with device-tree clock name.

Function to regiter bypass clocks is removed.

Input parameters from meson aoclk data structure are deprecated and then
deleted since all aoclk files are migrated.

Signed-off-by: Alexandre Mergnat <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>

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